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1. introduction this data sheet describes the functionality of the mfrc500 integr ated circuit (ic). it includes the functional and electrical spec ifications and from a system and hardware viewpoint gives detailed information on how to design-in the device. remark: the mfrc500 supports all variants of the mifare classic, mifare 1k and mifare 4k rf identificat ion protocols. to aid readability th roughout this data sheet, the mifare classic, mifare 1k and mifare 4k products and protocols have the generic name mifare. 2. general description the mfrc500 is a highly integrated read er ic for contactless communication at 13.56 mhz. the mfrc500 reader ic provides: ? outstanding modulation and demodulation for passive contactless communication ? a wide range of methods and protocols ? pin compatibility with the clrc63 2, mfrc530, mfrc531 and slrc400 all protocol layers of the iso/iec 14443 a are supported the receiver module provides a robust and efficient demodulation/decoding circuitry implementation for compatible transponder signals (see section 9.10 on page 30 ). the digital module, manages the complete iso/iec 14443 a standard framing and error detection (parity and crc). in addition, it sup ports the fast crypto1 security algorithm for authenticating the mifare products (see section 9.12 on page 35 ). the internal transmitter module ( section 9.9 on page 27 ) can directly drive an antenna designed for a proximity operating distance up to 100 mm without any additional active circuitry. a parallel interface can be directly connected to any 8-bit microprocessor to ensure reader/terminal design flexibility. mfrc500 the "original" mifare reader solution rev. 3.4 ? 11 february 2014 048034 product data sheet company public
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 2 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 3. features and benefits 3.1 general ? highly integrated analog circuitry for demodulating and decoding card response ? buffered output drivers enable antenna c onnection using the mi nimum of external components ? proximity operating distance up to 100 mm ? supports the iso/iec 14443 a standard, parts 1 to 4 ? supports mifare classic protocol ? crypto1 and secure non-volatile internal key memory ? pin-compatible with the clrc632, mfrc530, mfrc531 and the slrc400 ? parallel microprocessor interface with internal address latch and irq line ? flexible interrupt handling ? automatic detection of parallel microprocessor interface type ? 64-byte send and receive fifo buffer ? hard reset with low power function ? software triggered power-down mode ? programmable timer ? unique serial number ? user programmable start-up configuration ? bit-oriented and byte oriented framing ? independent power supply pins for analog, digital and transmitter modules ? internal oscillator buffer optimized for low phase jitter enables 13.56 mhz quartz connection ? clock frequency filtering ? 3.3 v operation for transmitter in short range and proximity applications 4. applications ? electronic payment systems ? identification systems ? access control systems ? subscriber services ? banking systems ? digital content systems
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 3 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 5. quick reference data 6. ordering information table 1. quick reference data symbol parameter conditions min typ max unit t amb ambient temperature ? 40 - +150 ?c t stg storage temperature ? 40 - +150 ?c v ddd digital supply voltage ? 0.5 +5 +6 v v dda analog supply voltage ? 0.5 +5 +6 v v dd(tvdd) tvdd supply voltage ? 0.5 +5 +6 v ?v i ? input voltage (absolute value) on any digital pin to dvss ? 0.5 - v ddd + 0.5 v on pin rx to avss ? 0.5 - v dda + 0.5 v i li input leakage current ? 1.0 - +1.0 ma i dd(tvdd) tvdd supply current continuous wave - - 150 ma table 2. ordering information type number package name description version MFRC50001T/0fe so32 plastic small outline pack age; 32 leads; body width 7.5 mm sot287-1
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 4 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 7. block diagram fig 1. mfrc500 block diagram 001aaj629 fifo control 64-byte fifo master key buffer crypto1 unit control register bank nwr nrd ncs ale a0 a1 a2 10 11 9 21 22 23 24 13 14 15 16 17 18 19 20 ad0 to ad7/d0 to d7 state machine command register programmable timer interrupt control crc16/crc8 generation and check parallel/serial converter bit counter parity generation and check frame generation and check serial data switch bit decoding bit encoding 32 16-byte eeprom eeprom access control 32-bit pseudo random generator amplitude rating clock generation, filtering and distribution oscillator level shifters correlation and bit decoding reference voltage q-channel amplifier q-channel demodulator i-channel amplifier analog test multiplexer i-channel demodulator parallel interface control (including automatic interface detection and synchronisation) voltage monitor and power on detect dvdd rstpd q-clock generation transmitter control gnd gnd tx1 tx2 tvss rx aux vmid tvdd 57 8 29 27 30 6 v v power on detect oscin avdd avss oscout irq mfin mfout dvss 25 31 1 26 28 32 2 3 4 12 reset control power down control
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 5 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 8. pinning information 8.1 pin description fig 2. mfrc500 pin configuration mfrc500 oscin oscout irq rstpd mfin vmid mfout rx tx1 avss tvdd aux tx2 avdd tvss dvdd ncs a2 nwr/r/nw/nwrite a1 nrd/nds/ndstrb a0/nwait dvss ale/as/nastrb ad0/d0 d7/ad7 ad1/d1 d6/ad6 ad2/d2 d5/ad5 ad3/d3 d4/ad4 001aal483 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 20 19 22 21 24 23 26 25 32 31 30 29 28 27 table 3. pin description pin symbol type [1] description 1 oscin i oscillator/clock inputs: crystal oscillator input to the oscillator?s inverting amplifier externally generated clock input; f clk(ext) = 13.56 mhz 2 irq o interrupt request: generates an output signaling an interrupt event 3 mfin i iso/iec 14443 a mifare serial data interface input 4 [2] mfout o serial data iso/iec 14443 a output 5 tx1 o transmitter 1 modulated carrier output; 13.56 mhz 6 tvdd p transmitter power supply for the tx1 and tx2 output stages 7 tx2 o transmitter 2 modulated carrier output; 13.56 mhz 8 tvss g transmitter ground for the tx1 and tx2 output stages 9 ncs i not chip select input is used to sele ct and activate the mfrc500?s microprocessor interface 10 [3] nwr i not write input generates the strobe signal for writing data to the mfrc500 registers when applied to pins d0 to d7 r/nw i read not write input is used to switch between read or write cycles nwrite i not write input selects the read or write cycle to be performed 11 [3] nrd i not read input generates the strobe signal for reading data from the mfrc500 registers when applied to pins d0 to d7 nds i not data strobe input generates the st robe signal for the read and write cycles ndstrb i not data strobe input generates the strobe signal for the read and write cycles
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 6 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution [1] pin types: i = input, o = output, i/o = input/output, p = power and g = ground. [2] the slrc400 uses pin name sigout for pin mfout. the mfrc500 f unctionality includes test functi ons for the slrc400 using pin mfout. [3] these pins provide different functionality depending on the selected mi croprocessor inte rface type (see section 9.1 on page 7 for detailed information). 12 dvss g digital ground 13 to 20 [3] d0 to d7 i/o 8-bit bidirectional data bus input/output on pins d0 to d7 ad0 to ad7 i/o 8-bit bidirectional address and data bus input/output on pins ad0 to ad7 21 [3] ale i address latch enable input for pins ad0 to ad5; high latches the internal address as i address strobe input for pins ad0 to ad5; high latches the internal address nastrb i not address strobe input for pins ad0 to ad5; low latches the internal address 22 [3] a0 i address line 0 is the address register bit 0 input nwait o not wait output: low starts an access cycle high ends an access cycle 23 a1 i address line 1 is the address register bit 1 input 24 [3] a2 i address line 2 is the address register bit 2 input 25 dvdd p digital power supply 26 avdd p analog power supply for pins oscin, oscout, rx, vmid and aux 27 aux o auxiliary output is used to generate a nalog test signals. the output signal is selected using the testanaselect r egister?s testanao utsel[4:0] bits 28 avss g analog ground 29 rx i receiver input is used as the card response input. the carrier is load modulated at 13.56 mhz, drawn from the antenna circuit 30 vmid p internal reference voltag e pin provides the internal reference voltage as a supply remark: it must be connected to a 100 nf block capacitor connected between pin vmid and ground 31 rstpd i reset and power-down input: high: the internal current sinks are switched off, the oscillator is inhibited and the input pads are disconnected low (negative edge): start internal reset phase 32 oscout o crystal oscillator output for the oscillator?s inverting amplifier table 3. pin description ?continued pin symbol type [1] description
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 7 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9. functional description 9.1 digital interface 9.1.1 overview of supported microprocessor interfaces the mfrc500 supports direct interfacing to va rious 8-bit microprocessors. alternatively, the mfrc500 can be connected to a pc?s enhanced parallel port (epp). ta b l e 4 shows the parallel interface signals supported by the mfrc500. 9.1.2 automatic microprocessor interface detection after a power-on or hard reset, the mf rc500 resets the parallel microprocessor interface mode and detects the microprocessor interface type. the mfrc500 identifies the microprocessor interface using the logic levels on the control pins. this is performed using a combination of fixed pin connections and the dedicated initialization routine (see section 9.7.4 on page 25 ). table 4. supported microproces sor and epp interface signals bus control signals bus separated address and data bus multiplexed address and data bus separated read and write strobes control nrd, nwr, ncs n rd, nwr, ncs, ale address a0, a1, a2 ad0, ad1, ad2, ad3, ad4, ad5 data d0 to d7 ad0 to ad7 common read and write strobe control r/nw, nds, ncs r/nw, nds, ncs, as address a0, a1, a2 ad0, ad1, ad2, ad3, ad4, ad5 data d0 to d7 ad0 to ad7 common read and write strobe with handshake (epp) control - nwrite, ndstrb, nastrb, nwait address - ad0, ad1, ad2, ad3, ad4, ad5 data - ad0 to ad7
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 8 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.1.3 connection to different microprocessor types the connection to various micr oprocessor types is shown in ta b l e 5 . 9.1.3.1 separate read and write strobe refer to section 13.4.1 on page 86 for timing specification. table 5. connection scheme for detecting the parallel interface type mfrc500 pins parallel interface type and signals separated read/write strobe common read/write strobe dedicated address bus multiplexed address bus dedicated address bus multiplexed address bus multiplexed address bus with handshake ale high ale high as nastrb a2 a2 low a2 low high a1 a1 high a1 high high a0 a0 high a0 low nwait nrd nrd nrd nds nds ndstrb nwr nwr nwr r/nw r/nw nwrite ncs ncs ncs ncs ncs low d7 to d0 d7 to d0 ad7 to ad0 d 7 to d0 ad7 to ad0 ad7 to ad0 fig 3. connection to microprocessor: separate read and write strobes 001aak607 address bus (a3 to an) ncs a0 to a2 address bus (a0 to a2) d0 to d7 ale data bus (d0 to d7) high nrd read strobe (nrd) nwr write strobe (nwr) device address decoder non-multiplexed address ncs ad0 to ad7 ale multiplexed address/data (ad0 to ad7) address latch enable (ale) nrd read strobe (nrd) nwr write strobe (nwr) a2 low a1 high a0 high device address decoder
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 9 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.1.3.2 common read and write strobe refer to section 13.4.2 on page 87 for timing specification. 9.1.3.3 common read and writ e strobe: epp with handshake refer to section 13.4.3 on page 88 for timing specification. remark: in the epp standard a chip se lect signal is not defined. to cover this situation, the status of the ncs pin can be used to inhi bit the ndstrb signal. if this inhibitor is not used, it is mandatory that pin ncs is connected to pin dvss. remark: after each power-on or hard reset, the nwait signal on pin a0 is high-impedance. nwait is defined as the first negative edge applied to the nastrb pin after the reset phase. the mfrc500 does not support read address cycle. fig 4. connection to microprocessor: common read and write strobes 001aak608 address bus (a3 to an) ncs a0 to a2 address bus (a0 to a2) d0 to d7 ale data bus (d0 to d7) high nrd data strobe (nds) nwr read/write (r/nw) device address decoder non-multiplexed address ncs ad0 to ad7 ale multiplexed address/data (ad0 to ad7) address strobe (as) nrd data strobe (nds) nwr read/write (r/nw) a2 low a1 high a0 low device address decoder fig 5. connection to micropro cessor: epp common read/write strobe s and handshake 001aak609 low ncs ad0 to ad7 ale multiplexed address/data (ad0 to ad7) address strobe (nastrb) nrd data strobe (ndstrb) nwr read/write (nwrite) a2 high a1 high a0 nwait device
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 10 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.2 memory organiza tion of the eeprom table 6. eeprom memory organization diagram block byte address access memory content refer to position address 0 0 00h to 0fh r product information field section 9.2.1 on page 11 1 1 10h to 1fh r/w startup register initialization file section 9.2.2.1 on page 11 2 2 20h to 2fh r/w 3 3 30h to 3fh r/w register initialization file section 9.2.2.3 ? register initialization file (read/write) ? on page 13 4 4 40h to 4fh r/w 5 5 50h to 5fh r/w 6 6 60h to 6fh r/w 7 7 70h to 7fh r/w 8 8 80h to 8fh w keys for crypto1 section 9.2.3 on page 13 9990h to 9fhw 10 a a0h to afh w 11 b b0h to bfh w 12 c c0h to cfh w 13 d d0h to dfh w 14 e e0h to efh w 15 f f0h to ffh w 16 10 100h to 10fh w 17 11 110h to 11fh w 18 12 120h to 12fh w 19 13 130h to 13fh w 20 14 140h to 14fh w 21 15 150h to 15fh w 22 16 160h to 16fh w 23 17 170h to 17fh w 24 18 180h to 18fh w 25 19 190h to 19fh w 26 1a 1a0h to 1afh w 27 1b 1b0h to 1bfh w 28 1c 1c0h to 1cfh w 29 1d 1d0h to 1dfh w 30 1e 1e0h to 1efh w 31 1f 1f0h to 1ffh w
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 11 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.2.1 product information field (read only) [1] byte 4 contains the current version number. 9.2.2 register initialization files (read/write) register initialization from ad dress 10h to address 2fh is performed automatically during the initializing phase (see section 9.7.3 on page 25 ) using the startup register initialization file. in addition, the mfrc500 registers can be initialized using values from the register initialization file when the loadconfig command is executed (see section 11.4.1 on page 79 ). remark: the following points apply to initialization: ? the page register (addressed using 10h, 18h, 20h, 28h) is skipped and not initialized. ? presetxx registers: do not change. ? all reserved register bits set to logic 0: do not change. 9.2.2.1 startup register initialization file (read/write) the eeprom memory block address 1 and 2 contents are used to automatically set the register subaddresses 10h to 2fh during the initialization phase. the default values stored in the eeprom during pr oduction are shown in section 9.2.2.2 ? factory default startup register initialization file ? . table 7. product information field byte allocation byte 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 symbol crc internal product serial number - product type identification access r r r r r table 8. product information field byte description byte symbol access value description 15 crc r - the content of the product information field is secured using a crc byte which is checked during start-up 14 to 12 internal r - three bytes fo r internal trimming parameters 11 to 8 product serial number r - a unique four byte serial number for the device 7 to 5 reserved r - 4 to 0 product type identification r - the mfrc500 is a member of a new family of highly integrated reader ics. each member of the product family has a unique product type identification. the value of the product type identification is shown in table 9 . table 9. product type identification definition definition product type iden tification bytes byte01234 [1] value 30h 88h f8h 00h xxh
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 12 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution the byte assignment is shown in ta b l e 1 0 . 9.2.2.2 factory default startu p register initialization file during the production tests, the startup register initialization file is initialized using the default values shown in ta b l e 11 . during each power-up and initialization phase, these values are written to the mfrc500?s registers. table 10. byte assignment for register initialization at start-up eeprom byte address register address remark 10h (block 1, byte 0) 10h skipped 11h 11h copied ??? 2fh (block 2, byte 15) 2fh copied table 11. shipment content of startup configuration file eeprom byte address register address value symbol description 10h 10h 00h page free for user 11h 11h 58h txcontrol transmitter pins tx1 and tx2 are switched off, bridge driver configuration, modulator driven from internal digital circuitry 12h 12h 3fh cwconductance source resistance of tx1 and tx2 is set to minimum 13h 13h 3fh preset13 - 14h 14h 19h preset14 - 15h 15h 13h modwidth pulse width for miller pulse encoding is set to standard configuration 16h 16h 00h preset16 - 17h 17h 00h preset17 - 18h 18h 00h page free for user 19h 19h 73h rxcontrol1 iso/iec 14443 a is set and internal amplifier gain is maximum 1ah 1ah 08h decodercontrol bit-collisions always evaluate to high in the data bit stream 1bh 1bh adh bitphase bitphase[7:0] is set to standard configuration 1ch 1ch ffh rxthreshold minlevel[3:0] and colllevel[3:0] are set to maximum 1dh 1dh 00h preset1d - 1eh 1eh 41h rxcontrol2 use q-clock for the receiv er, automatic receiver off is switched on, decoder is driven from internal analog circuitry 1fh 1fh 00h clockqcontrol automatic q-clock calibration is switched on 20h 20h 00h page free for user 21h 21h 06h rxwait frame guard time is set to six bit-clocks 22h 22h 03h channelredundancy channel redundancy is set using iso/iec 14443 a 23h 23h 63h crcpresetlsb crc preset value is set using iso/iec 14443 a 24h 24h 63h crcpresetmsb crc preset value is set using iso/iec 14443 a 25h 25h 00h preset25 - 26h 26h 00h mfoutselect pin mfout is set low 27h 27h 00h preset27 - 28h 28h 00h page free for user
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 13 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.2.2.3 register initializa tion file (read/write) the eeprom memory content from block ad dress 3 to 7 can initialize register subaddresses 10h to 2fh when the loadconfig command is executed (see section 11.4.1 on page 79 ). this command requires the eeprom starting byte address as a two byte argument for the initialization procedure. the byte assignment is shown in ta b l e 1 2 . the register initialization file is large enough to hold values for two initialization sets and up to one block (16-byte) of user data. remark: the register initialization file can be read/written by users and these bytes can be used to store other user data. after each power-up, the default configuration enables the mifare and iso/iec 14443 a protocol. 9.2.3 crypto1 keys (write only) mifare security requires specific cryp tographic keys to encrypt data stream communication on the contactless interfac e. these keys are called crypto1 keys. 9.2.3.1 key format keys stored in the eeprom are written in a sp ecific format. each key byte must be split into lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble). each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. this format is a precondition for successful execution of the loadkeye2 (see section 11.6.1 on page 81 ) and loadkey commands (see section 11.6.2 on page 81 ). 29h 29h 08h fifolevel waterlevel[ 5:0] fifo buffer warning level is set to standard configuration 2ah 2ah 07h timerclock tprescaler[4:0] is set to standard configuration, timer unit restart function is switched off 2bh 2bh 06h timercontrol timer is started at the end of transmission, stopped at the beginning of reception 2ch 2ch 0ah timerreload treloadval ue[7:0]: the timer unit preset value is set to standard configuration 2dh 2dh 02h irqpinconfig pin irq is set to high-impedance 2eh 2eh 00h preset2e - 2fh 2fh 00h preset2f - table 11. shipment content of startup configuration file ?continued eeprom byte address register address value symbol description table 12. byte assignment for register initialization at startup eeprom byte address register address remark eeprom starting byte address 10h skipped eeprom + 1 starting byte address 11h copied ?? eeprom + 31 starting byte address 2fh copied
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 14 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution using this format, 12 bytes of eeprom memory are needed to st ore a 6-byte key. this is shown in figure 6 . example : the value for the key must be written to the eeprom. ? if the key was: a0h a1h a2h a3h a4h a5h then ? 5ah f0h 5ah e1h 5ah d2h 5ah c3h 5ah b4h 5ah a5h would be written. remark: it is possible to load data for other key formats into the eeprom key storage location. however, it is not possible to validate card authentic ation with data which will cause the loadkeye2 command (see section 11.6.1 on page 81 ) to fail. 9.2.3.2 storage of keys in the eeprom the mfrc500 reserves 384 by tes of memory in the eeprom for the crypto1 keys. no memory segmentation is used to mirror the 12-byte structure of ke y storage. thus, every byte of the dedicated memory area can be the start of a key. example : if the key loading cycle starts at the la st byte address of an eeprom block, (for example, key byte 0 is stored at 12fh), th e next bytes are stored in the next eeprom block, for example, key byte 1 is stored at 130h, byte 2 at 131h up to byte 11 at 13ah. based on the 384 bytes of memory and a single key needing 12 bytes, then up to 32 different keys can be stored in the eeprom. remark: it is not possible to load a key ex ceeding the eeprom byte location 1ffh. 9.3 fifo buffer an 8 ? 64 bit fifo buffer is used in the mfrc500 to act as a parallel-to -parallel converter. it buffers both the input and output data streams between the microprocessor and the internal circuitry of the mfrc500. this ma kes it possible to manage data streams up to 64 bytes long without needing to take timing constraints into account. 9.3.1 accessing the fifo buffer 9.3.1.1 access rules the fifo buffer input and output data bus is connected to the fifodata register. writing to this register stores one byte in the fifo buffer and increments the fifo buffer write pointer. reading from this register shows the fifo buffer contents stored at the fifo buffer read pointer and increments the fifo buffer read pointer. the distance between the write and read pointer can be obtained by reading the fifolength register. fig 6. key storage format 001aak640 0 (lsb) master key byte master key bits eeprom byte address example k7 k6 k5 k4 k7 k6 k5 k4 n 5ah k3 k2 k1 k0 k3 k2 k1 k0 n + 1 f0h 1 k7 k6 k5 k4 k7 k6 k5 k4 n + 2 5ah k3 k2 k1 k0 k3 k2 k1 k0 n + 3 e1h 5 (msb) k7 k6 k5 k4 k7 k6 k5 k4 n + 10 5ah k3 k2 k1 k0 k3 k2 k1 k0 n + 11 a5h
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 15 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution when the microprocessor star ts a command, the mfrc500 can still access the fifo buffer while the command is running. only one fifo buffer has been implemented which is used for input and output. therefore, the microprocessor must ensure that there are no inadvertent fifo buffer accesses. ta b l e 1 3 gives an overview of fifo buffer access during command processing. 9.3.2 controlling the fifo buffer in addition to writing to and reading from the fifo buffer, the fifo buffer pointers can be reset using the flushfifo bit. this changes the fifolength[6:0] value to zero, bit fifoovfl is cleared a nd the stored bytes are no longer acce ssible. this enables the fifo buffer to be written with another 64 bytes of data. 9.3.3 fifo buffer status information the microprocessor can get the following fifo buffer status data: ? the number of bytes stored in th e fifo buffer: bits fifolength[6:0] ? the fifo buffer full warning: bit hialert ? the fifo buffer empty warning: bit loalert ? the fifo buffer overflow warning: bit fifoovfl. remark: setting the flushfifo bit clears the fifoovfl bit. the mfrc500 can generate an interrupt signal when: ? bit loalertirq is set to logic 1 and bit loalert = logic 1, pin irq is activated. ? bit hialertirq is set to logic 1 and bit hialert = logic 1, pin irq activated. the hialert flag bit is set to logic 1 only when the waterlevel[5:0] bits or less can be stored in the fifo buffer. the trigger is generated by equation 1 : table 13. fifo buffer access active command fifo buffer remark ? p write ? p read startup - - idle - - transmit yes - receive - yes transceive yes yes the microprocessor has to know the state of the command (transmitting or receiving) writee2 yes - reade2 yes yes the microprocessor has to prepare the arguments, afterwards only reading is allowed loadkeye2 yes - loadkey yes - authent1 yes - authent2 - - loadconfig yes - calccrc yes -
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 16 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution (1) the loalert flag bit is set to logic 1 when th e fifolevel register?s waterlevel[5:0] bits or less are stored in the fifo buffer. the trigger is generated by equation 2 : (2) 9.3.4 fifo buffer registers and flags ta b l e 1 4 shows the related fifo buffer flags in alphabetic order. 9.4 interrupt request system the mfrc500 indicates interrupt events by sett ing the primarystatus register bit irq (see section 10.5.1.4 ? primarystatus register ? on page 45 ) and activating pin irq. the signal on pin irq can be used to interrupt the microprocessor using its interrupt handling capabilities ensuring efficient microprocessor software. 9.4.1 interrupt sources overview ta b l e 1 5 shows the integrated interrupt flags, related source and setting condition. the interrupt timerirq flag bit indicates an interrup t set by the timer unit. bit timerirq is set when the timer decrements from one down to zero (bit tautorestart disabled) or from one to the treloadvalue[7:0] wit h bit tautorestart enabled. bit txirq indicates interrupts from different sources and is set as follows: ? the transmitter automatically sets the bit txir q interrupt when it is active and its state changes from sending data to transmitting the end of frame pattern ? the crc coprocessor sets the bit txirq after all data from the fifo buffer has been processed indicated by bit crcready = logic 1 ? when eeprom programming is finished, the bit txirq is set and is indicated by bit e2ready = logic 1 the rxirq flag bit indicates an interrupt when the end of the received data is detected. the idleirq flag bit is set when a command finishes and the content of the command register changes to idle. hialert 64 fifolength ? ?? waterlevel ? = loalert fifolength waterlevel ? = table 14. associated fifo buffer registers and flags flags register name bit register address fifolength[6:0] fifolength 6 to 0 04h fifoovfl errorflag 4 0ah flushfifo control 0 09h hialert primarystatus 1 03h hialertien interrupten 1 06h hialertirq interruptrq 1 07h loalert primarystatus 0 03h loalertien interrupten 0 06h loalertirq interruptrq 0 07h waterlevel[5:0] fifolevel 5 to 0 29h
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 17 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution when the fifo buffer reaches the high-level indicated by the waterlevel[5:0] value (see section 9.3.3 on page 15 ) and bit hialert = logic 1, then the hialertirq flag bit is set to logic 1. when the fifo buffer reaches the low-level indicated by the waterlevel[5:0] value (see section 9.3.3 and bit loalert = logic 1, then loalertirq flag bit is set to logic 1. 9.4.2 interrupt request handling 9.4.2.1 controlling interrupts and getting their status the mfrc500 informs the microprocessor about the interrupt request source by setting the relevant bit in the interruptrq register. the relevance of each interrupt request bit as source for an interrupt can be masked by the interrupten register interrupt enable bits. if an interrupt re quest flag is set to logic 1 (showing that an interrupt request is pending) and the corresponding interrupt enable flag is se t, the primarystatus r egister irq flag bit is set to logic 1. different interrupt sources can activate simultaneously and because of this, all interrupt request bits are or?ed, coupled to the irq flag and then forwarded to pin irq. 9.4.2.2 accessing the interrupt registers the interrupt request bits are automatically set by the mfrc500?s internal state machines. in addition, the microprocessor can also set or clear the interrupt request bits as required. a special implementation of the interruptrq and interrupten registers enables changing an individual bit status without influencing any other bits. if an interrup t register is set to logic 1, bit setixx and the specific bit must both be set to logic 1 at the same time. vice versa, if a specific interrupt flag is cleared, zero must be written to the setixx and the interrupt register address must be set to logic 1 at the same time. if a content bit is not changed during the setting or clearing phase, zero must be written to the specific bit location. table 15. interrupt sources interrupt flag interrupt source trigger action timerirq timer unit timer counts from 1 to 0 txirq transmitter a data stream, transmitted to the card, ends crc coprocessor all data from the fifo buffer has been processed eeprom all data from the fifo buffer has been programmed rxirq receiver a data stream, received from the card, ends idleirq command register command execution finishes hialertirq fifo buffer fifo buffer is full loalertirq fifo buffer fifo buffer is empty table 16. interrupt control registers register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 interrupten setien reserved timerien txien rxien idleien hialertien loalertien interruptrq setirq reserved timerirq txirq rxirq idleirq hialertirq loalertirq
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 18 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution example: writing 3fh to the interruptrq register clears all bits. setirq is set to logic 0 while all other bits are set to logic 1. writing 81h to the interruptrq register sets loalertirq to logic 1 and leaves all other bits unchanged. 9.4.3 configuration of pin irq the logic level of the irq flag bit is visible on pin irq. the signal on pin irq can also be controlled using the following irqpinconfig register bits. ? bit irqinv: the signal on pin irq is equal to th e logic level of bit irq when this bit is set to logic 0. when set to logic 1, the signal on pin irq is inverted with respect to bit irq. ? bit irqpushpull: when set to logic 1, pin irq has cmos output characteristics. when it is set to logic 0, it is an open-drain output which requires an external resistor to achieve a high-level at pin irq. remark: during the reset phase (see section 9.7.2 on page 25 ) bit irqinv is set to logic 1 and bit irqpushpull is set to logic 0. this results in a high-impedance on pin irq. 9.4.4 register overview interrupt request system ta b l e 1 7 shows the related interrupt request system flags in alphabetically. table 17. associated interrupt request system registers and flags flags register name bit register address hialertien interrupten 1 06h hialertirq interruptrq 1 07h idleien interrupten 2 06h idleirq interruptrq 2 07h irq primarystatus 3 03h irqinv irqpinconfig 1 07h irqpushpull irqpinconfig 0 07h loalertien interrupten 0 06h loalertirq interruptrq 0 07h rxien interrupten 3 06h rxirq interruptrq 3 07h setien interrupten 7 06h setirq interruptrq 7 07h timerien interrupten 5 06h timerirq interruptrq 5 07h txien interrupten 4 06h txirq interruptrq 4 07h
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 19 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.5 timer unit the timer derives its clock from the 13.56 mhz on-board chip clock. the microprocessor can use this timer to manage timing-relevant tasks. the timer unit may be used in one of the following configurations: ? timeout counter ? watchdog counter ? stopwatch ? programmable one shot ? periodical trigger the timer unit can be used to measure the time interval between two events or to indicate that a specific timed event occurred. the timer is triggered by events but does not influence any event (e.g. a time-out during data receiving does not automatically influence the reception process). several timer related flags can be set and these flags can be used to generate an interrupt. 9.5.1 timer unit implementation 9.5.1.1 timer unit block diagram figure 7 shows the block diagram of the timer module.
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 20 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution the timer unit is designed, so that events wh en combined with enabling flags start or stop the counter. for example, setting bit tstarttxbegin = logic 1 enables control of received data with the timer unit. in addition, the first received bit is indicated by the txbegin event. this combination starts the counte r at the defined treloadvalue[7:0]. the timer stops automatically when the counter va lue is equal to zero or if a defined stop event happens. 9.5.1.2 controlling the timer unit the main part of the timer unit is a down count er. as long as the down counter value is not zero, it decrements its value with each timer clock cycle. if the tautorestart flag is enabled, the timer does not decrement down to zero. on reaching value 1, the timer reloads the next clock function with the treloadvalue[7:0]. the timer is started immediately by loading a value from the timerreload register into the counter module. this is activated by one of the following events: fig 7. timer module block diagram 001aak611 txend event tautorestart trunning tstarttxend tstartnow s rq start counter/ parallel load stop counter tprescaler[4:0] timervalue[7:0] counter = 0 ? to interrupt logic: timerirq parallel out parallel in treloadvalue[7:0] clock divider counter module (x x ? 1) tstopnow txbegin event tstarttxbegin tstoprxend rxend event tstoprxbegin 13.56 mhz to parallel interface rxbegin event q
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 21 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution ? transmission of the first bit to the card (txbegin event) with bit tstarttxbegin = logic 1 ? transmission of the last bit to the card (txend event) with bit tstarttxend = logic 1 ? bit tstartnow is set to logic 1 by the microprocessor remark: every start event reloads the timer from the timerreload register which re-triggers the timer unit. the timer can be configured to stop on one of the following events: ? receipt of the first valid bit from the card (rxbegin event) with bit tstoprxbegin = logic 1 ? receipt of the last bit from the card (rxend event) with bit tstoprxend = logic 1 ? the counter module has decremented down to zero and bit tautorestart = logic 0 ? bit tstopnow is set to logic 1 by the microprocessor. loading a new value, e.g. zero, into the timerreload register or changing the timer unit while it is counting will not immediately influe nce the counter. in both cases, this is because this register only affects th e counter content after a start event. if the counter is stopped when bit tstopnow is set, no timerirq is flagged. 9.5.1.3 timer unit clock and period the timer unit clock is derived from the 13.56 mhz on-board chip clock using the programmable divider. clock selection is made using the timerclock register tprescaler[4:0] bits based on equation 3 : (3) the values for the tprescaler[4:0] bits are between 0 and 21 which results in a minimum periodic time (t timerclock ) of between 74 ns and 150 ms. the time period elapsed since the la st start event is calculated using equation 4 : (4) this results in a minimum time period (t timer ) of between 74 ns and 40 s. 9.5.1.4 timer unit status the secondarystatus register?s trunning bit shows the timer?s status. configured start events start the timer at the treloadvalue[7:0] and change the status flag trunning to logic 1. conversely, configured stop events stop the timer and set the trunning status flag to logic 0. as long as status flag trunning is set to logic 1, the timervalue register changes on the next timer unit clock cycle. the timervalue[7:0] bits can be read directly from the timervalue register. f timerclock 1 t timerclock --------------------------- 2 tprescaler 13.56 -------------------------- mhz ?? == t timer treloadvalue timervalue ? f timerclock ----------------------------------------------------------------------------- s ?? =
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 22 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.5.2 using the timer unit functions 9.5.2.1 time-out and watchdog counters after starting the timer using treloadvalue[7: 0], the timer unit decrements the timervalue register beginning with a given start event. if a given stop event occurs, such as a bit being received from the card, the timer un it stops without generating an interrupt. if a stop event does not occur, such as the card not answering within the expected time, the timer unit decrements down to zero and generates a timer interrupt request. this signals to the microprocessor the expected ev ent has not occurred within the given time (t timer ). 9.5.2.2 stopwatch the time (t timer ) between a start and stop event is me asured by the microprocessor using the timer unit. setting the treloadvalue register triggers the timer which in turn, starts to decrement. if the defined stop event occurs, the timer stops. the time between start and stop is calculated by the microprocessor using equation 5 when the time does not decrement down to zero. (5) 9.5.2.3 programmable one shot timer and periodic trigger programmable one shot timer: the microprocessor starts the timer unit and waits for the timer interrupt. the in terrupt occurs after the time specified by t timer . periodic trigger: if the microprocessor sets the tautores tart bit, it generates an interrupt request after every t timer cycle. ? t treload value timervalue ? ?? t timer ? =
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 23 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.5.3 timer unit registers ta b l e 1 8 shows the related flags of the timer unit in alphabetical order. 9.6 power reduction modes 9.6.1 hard power-down hard power-down is enabled when pin rstpd is high. this turns off all internal current sinks including the oscillator. all digital in put buffers are se parated from the input pads and defined internally (except pin rs tpd itself). the output pins are frozen at a given value. the status of all pins during a hard power-down is shown in table 19 . table 18. associated timer unit registers and flags flags register name bit register address tautorestart timerclock 5 2ah timervalue[7:0] timervalue 7 to 0 0ch treloadvalue[7:0] timerreload 7 to 0 2ch tprescaler[4:0] timerclock 4 to 0 2ah trunning secondarystatus 7 05h tstartnow control 1 09h tstarttxbegin timercontrol 0 2bh tstarttxend timercontrol 1 2bh tstopnow control 2 09h tstoprxbegin timercontrol 2 2bh tstoprxend timercontrol 3 2bh table 19. signal on pins during hard power-down symbol pin type description oscin 1 i not separated from input, pulled to avss irq 2 o high-impedance mfin 3 i separated from input mfout 4 o low tx1 5 o high, if bit tx1rfen = logic 1 low, if bit tx1rfen = logic 0 tx2 7 o high, only if bit tx2rfen = logic 1 and bit tx2inv = logic 0 otherwise low ncs 9 i separated from input nwr 10 i separated from input nrd 11 i separated from input d0 to d7 13 to 20 i/o separated from input ale 21 i separated from input a0 22 i/o separated from input a1 23 i separated from input a2 24 i separated from input aux 27 o high-impedance
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 24 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.6.2 soft power-down mode soft power-down mode is entered immediately using the control register bit powerdown. all internal current sink s, including the oscillator buffer, ar e switched off. the digital input buffers are not separated from the input pads an d keep their functionality. in addition, the digital output pins do not change their state. after resetting the control register bit powerdown, the bit indicating soft power-down mode is only cleared after 512 clock cycles. resetting it does not immediately clear it. the powerdown bit is automatically cleared wh en the soft power-down mode is exited. remark: when the internal oscillator is used, time (t osc ) is required for the oscillator to become stable. this is because the internal oscillator is supplied by v dda and any clock cycles will not be detected by the internal logic until v dda is stable. 9.6.3 standby mode the standby mode is immediately entered when the control register standby bit is set. all internal current sinks, including the internal digital clock buffer are switched off. however, the oscillator buffer is not switched off. the digital input buffers are not separated by the input pads, keeping their functionality and the digital output pi ns do not change their state. in addition, the oscillator does not need time to wake-up. after resetting the control register standby bit, it takes four clock cycles on pin oscin for standby mode to exit. resetting bit standby does not immediately clear it. it is automatically cleared when the standby mode is exited. 9.6.4 automatic receiver power-down it is a power saving feature to switch off the re ceiver circuit when it is not needed. setting bit rxautopd = logic 1, automatically powers do wn the receiver when it is not in use. setting bit rxautopd = logic 0, keeps th e receiver continuously powered up. rx 29 i not changed vmid 30 a pulled to v dda rstpd 31 i not changed oscout 32 o high table 19. signal on pins during hard power-down ?continued symbol pin type description
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 25 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.7 startup phase the events executed during the startup phase are shown in figure 8 . 9.7.1 hard power-down phase the hard power-down phase is active during the following cases: ? a power-on reset (por) caused by power-up on pins dvdd or avdd activated when v ddd or v dda is below the relevant analog/digital reset threshold. ? a high-level on pin rstpd which is active while pin rstpd is high. the high level period on pin rstpd must be at least 100 ? s (t pd ? 100 ? s). shorter phases will not necessarily result in the reset phase (t reset ). the rising or falling edge slew rate on pin rstpd is not critical because pin rstpd is a schmitt trigger input. 9.7.2 reset phase the reset phase automa tically follows the hard power- down. once the oscillator is running stably, the reset phase takes 512 cl ock cycles. during the reset phase, some register bits are preset by hardware. the respective reset values are given in the description of each register (see section 10.5 on page 43 ). remark: when the internal oscillator is used, time (t osc ) is required for the oscillator to become stable. this is because the internal oscillator is supplied by v dda and any clock cycles will not be detected by the internal logic until v dda is stable. 9.7.3 initialization phase the initialization phase automat ically follows the reset phase and takes 128 clock cycles. during the initializing phase the content of the eeprom blocks 1 and 2 is copied into the register subaddresses 10h to 2fh (see section 9.2.2 on page 11 ). remark: during the production test, the mfrc500 is initialized with default configuration values. this reduces the microprocessor?s configuration time to a minimum. 9.7.4 initializing the parallel interface type a different initialization sequence is used for each microprocessor. this enables detection of the correct microprocessor interface type and synchronization of the microprocessor?s and the mfrc500?s start-up. see section 9.1.3 on page 8 for detailed information on the different connections for each microprocessor interface type. during startup phase, the command value is set to 3fh once the oscillator attains clock frequency stability at an amplit ude of > 90 % of t he nominal 13.56 mhz cl ock frequency. at the end of the initialization phase, the mfrc 500 automatically switches to idle and the command value changes to 00h. fig 8. the startup procedure 001aak613 startup phase states t rstpd t reset t init hard power- down phase reset phase initialising phase ready
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 26 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution to ensure correct detection of the micropro cessor interface, the following sequence is executed: ? the command register is read until the 6-bit register value is 00h. on reading the 00h value, the internal initializ ation phase is complete and the mfrc500 is ready to be controlled ? write 80h to the page register to initialize the microprocessor interface ? read the command register. if it returns a va lue of 00h, the microprocessor interface was successfully initialized ? write 00h to the page registers to activate linear addressing mode. 9.8 oscillator circuit the clock applied to the mfrc500 acts as a time basis for the synchronous system encoder and decoder. the stabilit y of the clock frequency is an important factor for correct operation. to obtain highest performance, clock jitter must be as small as possible. this is best achieved by using the internal oscillator buffer wit h the recommend ed circuitry. if an external clock source is used, the clock signal must be applied to pin oscin. in this case, be very careful in optimi zing clock duty cycle and cl ock jitter. ensure the clock quality has been verified. it must meet the specifications described in section 13.4.4 on page 90 . remark: we do not recommend using an external clock source. fig 9. quartz clock connection 001aak614 13.56 mhz 15 pf 15 pf oscout oscin device
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 27 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.9 transmitter pins tx1 and tx2 the signal on pins tx1 and tx2 is the 13.56 mhz energy carrier modulated by an envelope signal. it can be used to drive an antenna directly, using minimal passive components for matching and filtering (see section 15.1 on page 91 ). to enable this, the output circuitry is designed with a very low- impedance source resistance. the txcontrol register is used to control the tx1 and tx2 signals. 9.9.1 configuring pins tx1 and tx2 tx1 pin configurations are described in ta b l e 2 0 . tx2 pin configurations are described in ta b l e 2 1 . table 20. pin tx1 configurations txcontrol register configuration envelope tx1 signal tx1rfen force100ask 0 x x low (gnd) 1 0 0 13.56 mhz carrier frequency modulated 1 0 1 13.56 mhz carrier frequency 110low 1 1 1 13.56 mhz energy carrier table 21. pin tx2 configurations txcontrol register configuration envelope tx2 signal tx2rfen force100ask tx2cw tx2inv 0x xxxlow 1 0 0 0 0 13.56 mhz carrier frequency modulated 1 0 0 0 1 13.56 mhz carrier frequency 1 0 0 1 0 13.56 mhz carrier frequency modulated, 180 ? phase-shift relative to tx1 1 0 0 1 1 13.56 mhz carrier frequency, 180 ? phase-shift relative to tx1 1 0 1 0 x 13.56 mhz carrier frequency 1 0 1 1 x 13.56 mhz carrier frequency, 180 ? phase-shift relative to tx1 11 000lo w 1 1 0 0 1 13.56 mhz carrier frequency 11 010hi gh 1 1 0 1 1 13.56 mhz carrier frequency, 180 ? phase-shift relative to tx1 1 1 1 0 x 13.56 mhz carrier frequency 1 1 1 1 x 13.56 mhz carrier frequency, 180 ? phase-shift relative to tx1
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 28 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.9.2 antenna operating distance versus power consumption using different antenna matching circuits (by varying the supply voltage on the antenna driver supply pin tvdd), it is possible to find the trade-off between maximum effective operating distance and power consumption. different antenna matching circuits are described in the application note ?mifare design of mfrc500 matching circuit and antennas? . 9.9.3 antenna driver output source resistance the output source conductance of pins tx1 and tx2 can be adjusted between 1 ? and 100 ? using the cwconductance register gscfgcw[5:0] bits. the output source conductance of pins tx1 and tx2 during the modulation phase can be adjusted between 1 ? and 100 ? using the modconductance register gscfgmod[5:0] bits. the values are relative to the reference resistance (r s(ref) ) which is measured during the production test and stored in the mfrc500 eeprom. it can be read from the product information field (see section 9.2.1 on page 11 ). the electrical specification can be found in section 13.3.3 on page 86 . 9.9.3.1 source resistance table table 22. tx1 and tx2 source resistance of n-chan nel driver transistor against gscfgcw or gscfgmod mant = mantissa; exp= exponent. gscfgcw, gscfgmod (decimal) exp gscfgcw , exp gscfgmod (decimal) mant gscfgcw , mant gscfgmod (decimal) r s(ref) (? ) gscfgcw, gscfgmod (decimal) exp gscfgcw , exp gscfgmod (decimal) mant gscfgcw , mant gscfgmod (decimal) r s(ref) (? ) 0 0 0 - 24 1 8 0.0652 16 1 0 - 25 1 9 0.0580 32 2 0 - 37 2 5 0.0541 48 3 0 - 26 1 10 0.0522 1 0 1 1.0000 27 1 11 0.0474 17 1 1 0.5217 51 3 3 0.0467 2 0 2 0.5000 38 2 6 0.0450 3 0 3 0.3333 28 1 12 0.0435 33 2 1 0.2703 29 1 13 0.0401 18 1 2 0.2609 39 2 7 0.0386 4 0 4 0.2500 30 1 14 0.0373 5 0 5 0.2000 52 3 4 0.0350 19 1 3 0.1739 31 1 15 0.0348 6 0 6 0.1667 40 2 8 0.0338 7 0 7 0.1429 41 2 9 0.0300 49 3 1 0.1402 53 3 5 0.0280 34 2 2 0.1351 42 2 10 0.0270 20 1 4 0.1304 43 2 11 0.0246 8 0 8 0.1250 54 3 6 0.0234 9 0 9 0.1111 44 2 12 0.0225 21 1 5 0.1043 45 2 13 0.0208
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 29 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.9.3.2 calculating the relative source resistance the reference source resistance r s(ref) can be calculated using equation 6 . (6) the reference source resistance (r s(ref) ) during the modulation phase can be calculated using modconductance register?s gscfgmod[5:0]. 9.9.3.3 calculating the effective source resistance wiring resistance (r s(wire) ): wiring and bonding add a constant offset to the driver resistance that is relevant when pins tx1 and tx2 are switched to low-impedance. the additional resistance for pin tx1 (r s(wire)tx1 ) can be set approximately as shown in equation 7 . (7) effective resistance (r sx ): the source resistances of t he driver transistors (rsmaxp byte) read from the product information field (see section 9.2.1 on page 11 ) are measured during the production test with cwconductance register?s gscfgcw[5:0] = 01h. to calculate the driver resistance for a specific value set in gscfgmod[5:0], use equation 8 . (8) 9.9.4 pulse width the envelope carries the data signal information that is transmitted to the card. it is an encoded data signal based on the miller co de. in addition, each pause of the miller encoded signal is again encoded as a pulse of a fixed width. the width of the pulse is 10 0 10 0.1000 55 3 7 0.0200 11 0 11 0.0909 46 2 14 0.0193 35 2 3 0.0901 47 2 15 0.0180 22 1 6 0.0870 56 3 8 0.0175 12 0 12 0.0833 57 3 9 0.0156 13 0 13 0.0769 58 3 10 0.0140 23 1 7 0.0745 59 3 11 0.0127 14 0 14 0.0714 60 3 12 0.0117 50 3 2 0.0701 61 3 13 0.0108 36 2 4 0.0676 62 3 14 0.0100 15 0 15 0.0667 63 3 15 0.0093 table 22. tx1 and tx2 source resistance of n-chan nel driver transistor against gscfgcw or gscfgmod ?continued mant = mantissa; exp= exponent. gscfgcw, gscfgmod (decimal) exp gscfgcw , exp gscfgmod (decimal) mant gscfgcw , mant gscfgmod (decimal) r s(ref) (? ) gscfgcw, gscfgmod (decimal) exp gscfgcw , exp gscfgmod (decimal) mant gscfgcw , mant gscfgmod (decimal) r s(ref) (? ) r sref ?? 1 mant gscfgcw 77 40 ----- - ?? ?? exp gscfgcw ? -------------------------------------------------------------------------------- = r swire ?? tx1 500 m ?? r sx r sref ?? maxp r swire ?? tx1 ? ?? r srel ?? r swire ?? tx1 + ?
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 30 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution adjusted using the modwidth register. the pulse width (t w ) is calculated using equation 9 where the frequency constant (f clk ) = 13.56 mhz. (9) 9.10 receiver circuit the mfrc500 uses an integrated quadrature de modulation circuit enabling it to extract the iso/iec 14443 a compliant subcarrier from the 13.56 mhz ask modulated signal applied to pin rx. the quadrature demodulator uses two differ ent clocks (q-clock and i-clock) with a phase-shift of 90 ? between them. both resulting subcarri er signals are amplified, filtered and forwarded to the correlation circuitry. th e correlation results are evaluated, digitized and then passed to the digital circuitry. various adjustments can be made to obtain optimum performance for all processing units. 9.10.1 receiver circuit block diagram figure 10 shows the block diagram of the receiver circuit. the receiving process can be broken down in to several steps. quadrature demodulation of the 13.56 mhz carrier signal is performed. to achieve the optimum perf ormance, automatic q-clock calibration is recommended (see section 9.10.2.1 on page 31 ). the demodulated signal is amplified by an adjustable amplifier. a correlation circuit calculates the degree of similarity betwee n the expected and the received signal. the bitphase register enables correlation interval po sition alignment with the received signal?s bit grid. in the evaluation and digitizer circui try, the valid bits are detected and the digital results are sent to the fifo buffer. several tuning steps are possible for this circuit. the signal can be observed on its way through the receiver as shown in figure 10 . one signal at a time can be routed to pin aux usin g the testanaselect register as described in section 15.2.2 on page 96 . t w 2 modwidth 1 + f clk ------------------------------------ - = fig 10. receiver circuit block diagram 001aak615 clkqdelay[4:0] clkqcalib clkq180deg bitphase[7:0] correlation circuitry evaluation and digitizer circuitry minlevel[3:0] colllevel[3:0] rxwait[7:0] rcvclksell s_valid s_data s_coll s_clock gain[1:0] to testanaoutsel clock i to q conversion i-clock q-clock 13.56 mhz demodulator rx vcorrdi vcorrni vcorrdq vcorrnq vevalr vevall vrxfollq vrxfolli vrxampi vrxampq
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 31 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.10.2 receiver operation in general, the default settings programmed in the startup initialization file are suitable for use with the mfrc500 to mifare card data communication. however, in some environments specific user setti ngs will achieve better performance. 9.10.2.1 automatic q-clock calibration the quadrature demodulation concept of the re ceiver generates a phase signal (i-clock) and a 90 ? phase-shifted quadrature signal (q -clock). to achieve the optimum demodulator performance, th e q-clock and the i-clock must be phase-shifted by 90 ? . after the reset phase, a calibration procedure is automatically performed. automatic calibration can be set-up to execute at the end of each transceive command if bit clkqcalib = logic 0. setting bit clkqcalib = l ogic 1 disables all automatic calibrations except after the reset sequence. automatic calibration can also be triggered by the software when bit clkqcalib has a logic 0 to logic 1 transition. remark: the duration of th e automatic q-clock calibration is 65 oscillator periods or approximately 4.8 ? s. the clockqcontrol register?s clkqdelay[4:0] value is proportional to the phase-shift between the q-clock and the i-clock. the clkq180deg status flag bit is set when the phase-shift between the q-clock and the i-clock is greater than 180 ? . remark: ? the startup configuration file enables automatic q-clock calibration after a reset ? if bit clkqcalib = logic 1, automatic calibration is not performed. leaving this bit set to logic 1 can be used to permanently disable automatic calibration. ? it is possible to write data to the clkqdel ay[4:0] bits using the microprocessor. the aim could be to disable automatic calibration and set the delay using the software. configuring the delay value us ing the software requires bit clkqcalib to have been previously set to logic 1 and a time interval of at least 4.8 ? s has elapsed. each delay value must be written with bit clkqcalib set to logic 1. if bit clkqcalib is logic 0, the configured delay value is overwritten by the next automatic calibration interval. 9.10.2.2 amplifier the demodulated signal must be amplified by the variable amplifier to achieve the best performance. the gain of the amplifiers c an be adjusted using the rxcontrol1 register gain[1:0] bits; see ta b l e 2 3 . fig 11. automatic q-clock calibration 001aak616 calibration impulse from reset sequence a rising edge initiates q-clock calibration clkqcalib bit calibration impulse from end of transceive command
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 32 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.10.2.3 correlation circuitry the correlation circuitry calculates the degr ee of matching between the received and an expected signal. the output is a measure of the amplitude of the expected signal in the received signal. this is done for both, the q and i-channels. the correlator provides two outputs for each of the two input channels, re sulting in a total of four output signals. the correlation circuitry needs the phase in formation for the incoming card signal for optimum performance. this information is defined for the microprocessor using the bitphase register. this value defines the pha se relationship between the transmitter and receiver clock in multiple s of the bitphase time (t bitphase )=1/13.56mhz. 9.10.2.4 evaluation a nd digitizer circuitry the correlation results are evaluated for each bit-half of the manchester encoded signal. the evaluation and digitizer circuit decides from the signal strengths of both bit-halves, if the current bit is valid ? if the bit is valid, it s value is identified ? if the bit is not valid, it is checked to identify if it contains a bit-collision select the following levels for opti mal using rxthreshold register bits: ? minlevel[3:0]: defines the minimum signal strength of the stronger bit-halve?s signal which is considered valid. ? colllevel[3:0]: defines the minimum signal strength relative to the amplitude of the stronger half-bit that has to be exceeded by the weaker half-bit of the manchester encoded signal to genera te a bit-collision. if the signal?s strength is below this value, logic 1 and logic 0 can be determined unequivocally. after data transmission, the card is not allow ed to send its response before a preset time period which is called the frame guard time in the iso/iec 14443 standard. the length of this time period is set using the rxwait regi ster?s rxwait[7:0] bits. the rxwait register defines when the receiver is switched on after data transmission to the card in multiples of one bit duration. if bit rcvclkseli is set to logic 1, the i-clock is used to clock the correlator and evaluation circuits. if bit rcvclkseli is set to logic 0, the q-clock is used. remark: it is recommended to use the q-clock. 9.11 serial signal switch the mfrc500 comprises two main blocks: table 23. gain factors for the internal amplifier see table 78 ? rxcontrol1 register bit descriptions ? on page 55 for additional information. register setting gain factor (db) (simulation results) 00 20 01 24 10 31 11 35
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 33 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution ? digital circuitry: comprising the state machines, encoder and decoder logic etc. ? analog circuitry : comprising the modulator, antenna drivers, receiver and amplification circuitry the interface between these two blocks can be configured so that the interface signals are routed to pins mfin and mfout. this make s it possible to connect the analog part of one mfrc500 to the digital part of another device. 9.11.1 serial signal switch block diagram figure 12 shows the serial signal switches. three different switches are implemented in the serial signal switch enabling the mfrc500 to be used in different configurations. the serial signal switch can also be used to check the transmitted and received data during the design-in phase or for test purposes. section 15.2.1 on page 94 describes the analog test signals and measurements at the serial signal switch. remark: the slr400 uses pin name sigout for pin mfout. the mfrc500 functionality includes the test mo des for the slrc400 using pin mfout. section 9.11.2 , section 9.11.2.1 and section 9.11.2.2 describe the relevant registers and settings used to configure and control the serial signal switch. 9.11.2 serial signal switch registers the rxcontrol2 register decodersource[1:0] bi ts define the input signal for the internal manchester decoder and are described in table 24 . fig 12. serial signal switch block diagram 3 001aak617 mfin mfout modulator driver (part of) analog circuitry subcarrier demodulator tx1 tx2 rx carrier demodulator 2 miller coder 1 out of 256 nrz or 1 out of 4 manchester decoder serial signal switch (part of) serial data processing decoder source[1:0] 2 modulator source[1:0] subcarrier demodulator serial data out 00 1 internal 2 manchester with subcarrier 3 0 1 2 3 4 5 6 0 1 envelope mfin 0 1 2 3 manchester manchester out serial data in 7 0 01 1 envelope transmit nrz manchester with subcarrier manchester reserved reserved mfoutselect[2:0] digital test signal signal to mfout
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 34 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution the txcontrol register modulatorsource[1:0] bits define the signal used to modulate the transmitted 13.56 mhz energy carrier. the modulated signal drives pins tx1 and tx2. the mfoutselect register mfoutselect[2:0] bits select the output signal which is to be routed to pin mfout. remark: to use the mfoutselect[2:0] bits, the testdigiselect register signaltomfout bit must be logic 0. 9.11.2.1 active antenna concept the mfrc500 analog and digital circuitry is accessed using pins mfin and mfout. ta b l e 2 7 lists the required settings. table 24. decodersource[1:0] values see table 88 on page 57 for additional information. number decodersource [1:0] input signal to decoder 0 00 constant 0 1 01 output of the analog part. th is is the default configuration 2 10 direct connection to pin mfin; expects an 847.5 khz subcarrier signal modulated by a manchester encoded signal 3 11 direct connection to pin mfin; expects a manchester encoded signal table 25. modulatorsource[1:0] values see table 88 on page 57 for additional information. number modulatorsource [1:0] input signal to modulator 0 00 constant 0 (energy carrier off on pins tx1 and tx2) 1 01 constant 1 (continuous energy carrier on pins tx1 and tx2) 2 10 modulation signal (envelope) from the internal encoder. this is the default configuration. 3 11 direct connection to mfin; expects a miller pulse coded signal table 26. mfoutselect[2:0] values see table 102 on page 60 for additional information. number mfoutselect [2:0] signal routed to pin mfout 0 000 constant low 1 001 constant high 2 010 modulation signal (envelope) from the internal encoder 3 011 serial data stream to be transmitted; the same as for mfoutselect[2:0] = 010 but not enc oded by the selected pulse encoder 4 100 output signal of the receiver circuit; card modulation signal regenerated and delayed 5 101 output signal of the subcarrier demodulator; manchester coded card signal 6110 reserved 7111 reserved
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 35 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution [1] the number column refers to the value in the number column of table 24 , table 25 and table 26 . two mfrc500 devices configured as described in ta b l e 2 7 can be connected to each other using pins mfout and mfin. 9.11.2.2 driving both rf parts it is possible to connect both passive and active antennas to a single ic. the passive antenna pins tx1, tx2 and rx are connected using the appropriate filter and matching circuit. at the same time an active antenna is connected to pins mfout and mfin. in this configuration, two rf parts can be driven , one after another, by one microprocessor. 9.12 mifare authentication and crypto1 the security algorithm used in the mifare products is called crypto1. it is based on a proprietary stream cipher with a 48-bit key length. to access data on mifare cards, knowledge of the key format is needed. th e correct key must be available in the mfrc500 to enable successful card authentication and access to the card?s data stored in the eeprom. after a card is selected as defined in iso/iec 14443 a standard, the user can continue with the mifare protocol. it is mandatory th at the card authentication is performed. crypto1 authentication is a 3- pass authentication which is automatically performed when the authent1 and authent2 commands are executed (see section 11.6.3 on page 82 and section 11.6.4 on page 82 ). during the card authentication procedure, th e security algorithm is initialized. after a successful authentication, communication with the mifare card is encrypted. 9.12.1 crypto1 key handling on execution of the authentication command, the mfrc500 reads the key from the key buffer. the key is always read from the key buffer and ensures crypto1 authentication commands do not require addressing of a key. the user must ensure the correct key is prepared in the key buffer before triggering card authentication. the key buffer can be loaded from: ? the eeprom using the loadkeye2 command (see section 11.6.1 on page 81 ) ? the microprocessor?s fifo buffer using the loadkey command (see section 11.6.2 on page 81 ). this is shown in figure 13 . table 27. register settings to enable use of the analog circuitry register number [1] signal mfrc500 pin analog circuitry settings modulatorsource 3 miller pulse encoded mfin mfoutselect 4 manchester encoded with subcarrier mfout decodersource x - - digital circuitry settings modulatorsource x - - mfoutselect 2 miller pulse encoded mfout decodersource 2 manchester encoded with subcarrier mfin
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 36 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 9.12.2 authentication procedure the crypto1 security algorithm enables authenti cation of mifare cards. to obtain valid authentication, the correct key has to be availa ble in the key buffer of the mfrc500. this can be ensured as follows: 1. load the internal key buffer by using the loadkeye2 (see section 11.6.1 on page 81 ) or the loadkey (see section 11.6.2 on page 81 ) commands. 2. start the authent1 command (see section 11.6.3 on page 82 ). when finished, check the error flags to obtain the command execution status. 3. start the authent2 command (see section 11.6.4 on page 82 ). when finished, check the error flags and bit crypto1on to obtain the command execution status. fig 13. crypto1 key handling block diagram 001aak624 fifo buffer from the microcontroller writee2 loadkey eeprom keys key buffer loadkeye2 during authent1 crypto1 module serial data stream out serial data stream in (plain) (encrypted)
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 37 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10. mfrc500 registers 10.1 register addressing modes three methods can be used to operate the mfrc500: ? initiating functions and controlling data by executing commands ? configuring the functional operation using a set of configuration bits ? monitoring the state of the mf rc500 by reading status flags the commands, configuration bits and fl ags are accessed using the microprocessor interface. the mfrc500 can internally address 64 registers using six address lines. 10.1.1 page registers the mfrc500 register set is segmented into eight pages contain eight registers each. a page register can always be addressed, irre spective of which page is currently selected. 10.1.2 dedicated address bus when using the mfrc500 with the dedicated address bus, the microprocessor defines three address lines using address pins a0, a1 and a2. this enables addressing within a page. to switch between registers in different pages a paging mechanism needs to be used. ta b l e 2 8 shows how the register address is assembled. 10.1.3 multiplexed address bus the microprocessor may define all six address lines at once using the mfrc500 with a multiplexed address bus. in this case either the paging mechanism or linear addressing can be used. ta b l e 2 9 shows how the register address is assembled. table 28. dedicated address bus: assembling the register address register bit: usepageselect register address 1 pageselect2 pageselect1 pageselect0 a2 a1 a0 table 29. multiplexed address bus: assembling the register address multiplexed address bus type usepage select register address paging mode 1 pageselect2 pageselect1 pageselect0 ad2 ad1 ad0 linear addressing 0 ad5 ad4 ad3 ad2 ad1 ad0
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 38 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.2 register bit behavior bits and flags for different registers behave differently, depending on their functions. in principle, bits with same behavior are grouped in common registers. ta b l e 3 0 describes the function of the access column in the register tables. table 30. behavior and designation of register bits abbreviation behavior description r/w read and write these bits can be read and written by the microprocessor. since they are only used for control, their content is not influenced by internal state machines. example: timerreload register may be read and written by the microprocessor. it will also be read by internal state machines but never changed by them. d dynamic these bits can be read a nd written by the microprocessor. nevertheless, they may also be written automatically by internal state machines. example: the command register changes its value automatically after the ex ecution of the command. r read only these registers hold flags which have a value determined by internal states only. example: the errorflag register cannot be written externally but shows internal states. w write only these registers are used for control only. they may be written by the microprocessor but cann ot be read. reading these registers returns an undefined value. example: the testanaselect register is used to determine the signal on pin aux however, it is not possible to read its content. 0, 1 or x generic value where applicable, the values 0 and 1 indicate the expected logic value for a given bit. where x is used, any logic value can be entered
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 39 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.3 register overview table 31. mfrc500 register overview sub address (hex) register name function refer to page 0: command and status 00h page selects the page register table 33 on page 43 01h command starts and stops command execution table 35 on page 44 02h fifodata input and outpu t of 64-byte fifo buffer table 37 on page 44 03h primarystatus receiver and transmit ter and fifo buffer status flags table 39 on page 45 04h fifolength number of bytes buffered in the fifo buffer table 41 on page 46 05h secondarystatus secondary status flags table 43 on page 46 06h interrupten enable and disable interrupt request control bits table 45 on page 47 07h interruptrq interrupt request flags table 47 on page 47 page 1: control and status 08h page selects the page register table 33 on page 43 09h control control flags for timer unit, power saving etc table 49 on page 48 0ah errorflag show the error status of the last command executed table 51 on page 49 0bh collpos bit position of the first bit- collision detected on the rf interface table 53 on page 50 0ch timervalue value of the timer table 55 on page 50 0dh crcresultlsb lsb of the crc coprocessor register table 57 on page 50 0eh crcresultmsb msb of the crc coprocessor register table 59 on page 51 0fh bitframing adjustments for bit oriented frames table 61 on page 51 page 2: transmitter and coder control 10h page selects the page register table 33 on page 43 11h txcontrol controls the operation of the antenna driver pins tx1 and tx2 table 63 on page 52 12h cwconductance selects the conductance of the antenna driver pins tx1 and tx2 table 65 on page 53 13h preset13 do not change these values table 67 on page 53 14h preset14 do not change these values table 69 on page 53 15h modwidth selects the modulation pulse width table 71 on page 54 16h preset16 do not change these values table 73 on page 54 17h preset17 do not change these values table 75 on page 54 page 3: receiver and decoder control 18 page selects the page register table 33 on page 43 19 rxcontrol1 controls receiver behavior table 77 on page 55 1a decodercontrol controls decoder behavior table 79 on page 55 1b bitphase selects the bit-phase between transmitter and receiver clock table 81 on page 56 1c rxthreshold selects thresholds for the bit decoder table 83 on page 56 1d preset1d do not change these values table 85 on page 56 1eh rxcontrol2 controls decoder and de fines the receiver input source table 87 on page 57 1fh clockqcontrol clock control for the 90 ? phase-shifted q-channel clock table 89 on page 57
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 40 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution page 4: rf timing and channel redundancy 20h page selects the page register table 33 on page 43 21h rxwait selects the interval after transmission before the receiver starts table 91 on page 58 22h channelredundancy selects the method and mode used to check data integrity on the rf channel table 93 on page 58 23h crcpresetlsb preset lsb value for the crc register table 95 on page 59 24h crcpresetmsb preset msb value for the crc register table 97 on page 59 25h preset25 do not change these values table 99 on page 59 26h mfoutselect selects internal signal applied to pin mfout, includes the msb of value timeslotperiod; see table 101 on page 60 table 101 on page 60 27h preset27 do not change these values table 103 on page 60 page 5: fifo, timer and irq pin configuration 28h page selects the page register table 33 on page 43 29h fifolevel defines the fifo buffer overflow and underflow warning levels table 41 on page 46 2ah timerclock selects the timer clock divider table 107 on page 61 2bh timercontrol selects the timer start and stop conditions table 109 on page 62 2ch timerreload defines the timer preset value table 111 on page 62 2dh irqpinconfig configures pin irq output stage table 113 on page 63 2eh preset2e do not change these values table 115 on page 63 2fh preset2f do not change these values table 116 on page 63 page 6: reserved registers 30h page selects the page register table 33 on page 43 31h reserved reserved table 117 on page 63 32h reserved reserved 33h reserved reserved 34h reserved reserved 35h reserved reserved 36h reserved reserved 37h reserved reserved page 7: test control 38h page selects the page register table 33 on page 43 39h reserved reserved table 118 on page 64 3ah testanaselect selects analog test mode table 119 on page 64 3bh reserved reserved table 121 on page 65 3ch reserved reserved table 122 on page 65 3dh testdigiselect selects digital test mode table 123 on page 65 3eh reserved reserved table 125 on page 66 3fh reserved reserved table 31. mfrc500 register overview ?continued sub address (hex) register name function refer to
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 41 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.4 mfrc500 register flags overview table 32. mfrc500 register flags overview flag(s) register bit address accesserr errorflag 5 0ah bitphase[7:0] bitphase 7 to 0 1bh clkq180deg clockqcontrol 7 1fh clkqcalib clockqcontrol 6 1fh clkqdelay[4:0] clockqcontrol 4 to 0 1fh collerr errorflag 0 0ah colllevel[3:0] rxthreshold 3 to 0 1ch collpos[7:0] collpos 7 to 0 0bh command[5:0] command 5 to 0 01h crc3309 channelredundancy 5 22h crc8 channelredundancy 4 22h crcerr errorflag 3 0ah crcpresetlsb[7:0] crcpresetlsb 7 to 0 23h crcpresetmsb[7:0] crcpresetmsb 7 to 0 24h crcready secondarystatus 5 05h crcresultmsb[7:0] crcresultmsb 7 to 0 0eh crcresultlsb[7:0] crcresultlsb 7 to 0 0dh crypto1on control 3 09h decodersource[1:0] rxcontrol2 1 to 0 1eh e2ready secondarystatus 6 05h err primarystatus 2 03h fifodata[7:0] fifodata 7 to 0 02h fifolength[6:0] fifolength 6 to 0 04h fifoovfl errorflag 4 0ah flushfifo control 0 09h framingerr errorflag 2 0ah gain[1:0] rxcontrol1 1 to 0 19h gscfgcw[5:0] cwconductance 5 to 0 12h hialert primarystatus 1 03h hialertien interrupten 1 06h hialertirq interruptrq 1 07h idleien interrupten 2 06h idleirq interruptrq 2 07h ifdetectbusy command 7 01h irq primarystatus 3 03h irqinv irqpinconfig 1 2dh irqpushpull irqpinconfig 0 2dh keyerr errorflag 6 0ah loalert primarystatus 0 03h
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 42 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution loalertien interrupten 0 06h loalertirq interruptrq 0 07h mfoutselect[2:0] mfoutselect 2 to 0 26h minlevel[3:0] rxthreshold 7 to 4 1ch modemstate[2:0] prima rystatus 6 to 4 03h modulatorsource[1:0] txcontrol 6 to 5 11h modwidth[7:0] modwidth 7 to 0 15h pageselect[2:0] page 2 to 0 00h, 08h, 10h, 18h, 20h, 28h, 30h and 38h parityen channelredundancy 0 22h parityerr errorflag 1 0ah parityodd channelredundancy 1 22h powerdown control 4 09h rcvclkseli rxcontrol2 7 1eh rxalign[2:0] bitframing 6 to 4 0fh rxautopd rxcontrol2 6 1eh rxcrcen channelredundancy 3 22h rxien interrupten 3 06h rxirq interruptrq 3 07h rxlastbits[2:0] secondarystatus 2 to 0 05h rxmultiple decodercontrol 6 1ah rxwait[7:0] rxwait 7 to 0 21h setien interrupten 7 06h setirq interruptrq 7 07h signaltomfout testdigiselect 7 3dh standby control 5 09h tautorestart timerclock 5 2ah testanaoutsel[4:0] testanaselect 3 to 0 3ah testdigisignalsel[6:0] testdigiselect 6 to 0 3dh timerien interrupten 5 06h timerirq interruptrq 5 07h timervalue[7:0] timervalue 7 to 0 0ch tprescaler[4:0] timerclock 4 to 0 2ah treloadvalue[7:0] timerreload 7 to 0 2ch trunning secondarystatus 7 05h tstarttxbegin timercontrol 0 2bh tstarttxend timercontrol 1 2bh tstartnow control 1 09h tstoprxbegin timercontrol 2 2bh tstoprxend timercontrol 3 2bh tstopnow control 2 09h table 32. mfrc500 register flags overview ?continued flag(s) register bit address
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 43 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5 register descriptions 10.5.1 page 0: command and status 10.5.1.1 page register selects the page register. tx1rfen txcontrol 0 11h tx2cw txcontrol 3 11h tx2inv txcontrol 3 11h tx2rfen txcontrol 1 11h txcrcen channelredundancy 2 22h txien interrupten 4 06h txirq interruptrq 4 07h txlastbits[2:0] bitframing 2 to 0 0fh usepageselect page 7 00h, 08h, 10h, 18h, 20h, 28h, 30h and 38h waterlevel[5:0] fifolevel 5 to 0 29h zeroaftercoll decodercontrol 5 1ah table 32. mfrc500 register flags overview ?continued flag(s) register bit address table 33. page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h) reset value: 1000 0000b, 80h bit allocation bit 7 6 5 4 3 2 1 0 symbol usepageselect 0000 pageselect[2:0] access r/w r/w r/w r/w r/w table 34. page register bit descriptions bit symbol value description 7 usepageselect 1 the value of pageselect[2: 0] is used as th e register address a5, a4, and a3. the lsbs of the register address are defined using the address pins or the internal address latch, respectively. 0 the complete content of the internal address latch defines the register address. the address pins are used as described in table 5 on page 8 . 6 to 3 0000 - reserved 2 to 0 pageselect[2:0] - when usepageselec t = logic 1, the value of pageselect is used to specify the register page (a5, a4 and a3 of the register address)
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 44 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.1.2 command register starts and stops the command execution. 10.5.1.3 fifodata register input and output of the 64 byte fifo buffer. table 35. command register (address: 01h) r eset value: x000 0000b, x0h bit allocation bit 7 6 5 4 3 2 1 0 symbol ifdetectbusy 0 command[5:0] access r r d table 36. command register bit descriptions bit symbol value description 7 ifdetectbusy shows the status of interface detection logic 0 interface detection finished successfully 1 interface detection ongoing 6 0 - reserved 5 to 0 command[5:0] - activates a co mmand based on the command code. reading this register shows which command is being executed. table 37. fifodata register (address: 02h) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol fifodata[7:0] access d table 38. fifodata register bit descriptions bit symbol description 7 to 0 fifodata[7:0] data input and output port for the internal 64-byte fifo buffer. the fifo buffer acts as a parallel in to parallel out converter for all data streams.
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 45 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.1.4 primarystatus register bits relating to receiver, transmitter and fifo buffer status flags. table 39. primarystatus register (address: 03 h) reset value: 0000 0101b, 05h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0 modemstate[2:0] irq err hialert loalert access r r r r r r table 40. primarystatus register bit descriptions bit symbol value status description 7 0 - reserved 6 to 4 modemstate[2:0] shows the stat e of the transmitter and receiver state machines: 000 idle neither the transmitter or receiver are operating; neither of them are started or have input data 001 txsof transmit start of frame pattern 010 txdata transmit data from the fifo buffer (or redundancy crc check bits) 011 txeof transmit end of frame (eof) pattern 100 gotorx1 intermediate state 1; receiver starts gotorx2 intermediate state 2; receiver finishes 101 preparerx waiting until the rx wait register time period expires 110 awaitingrx receiver activated; waiting for an input signal on pin rx 111 receiving receiving data 3 irq - shows any interrupt source requesting attention based on the interrupten register flag settings 2 err 1 any error flag in the errorflag register is set 1 hialert 1 the alert level for the number of bytes in the fifo buffer (fifolength[6:0]) is: otherwise value = logic 0 example: fifolength = 60, waterlevel = 4 then hialert = logic 1 fifolength = 59, waterlevel = 4 then hialert = logic 0 0 loalert 1 the alert level for number of bytes in the fifo buffer (fifolength[6:0]) is: otherwise value = logic 0 example: fifolength = 4, waterlevel = 4 then loalert = logic 1 fifolength = 5, waterlevel = 4 then loalert = logic 0 hialert 64 fifolength ? ?? waterlevel ? = loalert fifole ngth waterlevel ? =
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 46 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.1.5 fifolength register number of bytes in the fifo buffer. 10.5.1.6 secondarystatus register various secondary status flags. table 41. fifolength register (address: 04h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0 fifolength[6:0] access r r table 42. fifolength bit descriptions bit symbol description 7 0 reserved 6 to 0 fifolength[6:0] gives the number of by tes stored in the fifo buffer. writing increments the fifolength register value while reading decrements the fifolength register value table 43. secondarystatus register (address: 05h) reset value: 01100 000b, 60h bit allocation bit 7 6 5 4 3 2 1 0 symbol trunning e2ready crcready 00 rxlastbits[2:0] access r r r r r table 44. secondarystatus register bit descriptions bit symbol value description 7 trunning 1 the timer unit is running and the counter decrements the timervalue register on the next timer clock cycle 0 the timer unit is not running 6 e2ready 1 eeprom programming is finished 0 eeprom programming is ongoing 5 crcready 1 crc calculation is finished 0 crc calculation is ongoing 4 to 3 00 - reserved 2 to 0 rxlastbits[2:0] - shows the number of valid bits in the last received byte. if zero, the whole byte is valid
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 47 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.1.7 interrupten register control bits to enable and disable passing of interrupt requests. [1] this bit can only be set or cleared using bit setien. 10.5.1.8 interruptrq register interrupt re quest flags. table 45. interrupten register (address: 06h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol setien 0 timerien txien rxie n idleien hialertien loalertien access w r/w r/w r/w r/w r/w r/w r/w table 46. interrupten register bit descriptions bit symbol value description 7 setien 1 indicates that the marked bits in the interrupten register are set 0 clears the marked bits 6 0 - reserved 5 timerien - sends the timerirq timer interrupt request to pin irq [1] 4 txien - sends the txirq transmitter interrupt request to pin irq [1] 3 rxien - sends the rxirq receiver interrupt request to pin irq [1] 2 idleien - sends the idleirq idle interrupt request to pin irq [1] 1 hialertien - sends the hialertirq high alert interrupt request to pin irq [1] 0 loalertien - sends the loalertirq low alert interrupt request to pin irq [1] table 47. interruptrq register (address: 07h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol setirq 0 timerirq txirq rxirq idleirq hialertirq loalertirq access w r/w d d d d d d table 48. interruptrq register bit descriptions bit symbol value description 7 setirq 1 sets the marked bits in the interruptrq register 0 clears the marked bits in the interruptrq register 60 - reserved 5 timerirq 1 timer decrements the timervalue register to zero 0 timer decrements are still greater than zero 4 txirq 1 txirq is set to logic 1 if one of the following events occurs: transceive command; all data transmitted authent1 and authent2 commands; all data transmitted writee2 command; all data is programmed calccrc command; all data is processed 0 when not acted on by transceive, authent1, authent2, writee2 or calccrc commands 3 rxirq 1 the receiver terminates 0 reception still ongoing
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 48 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution [1] primarystatus register bit hialertirq stores this event and it can only be reset using bit setirq. 10.5.2 page 1: control and status 10.5.2.1 page register selects the page register; see section 10.5.1.1 ? page register ? on page 43 . 10.5.2.2 control register various control flags, for timer, power saving, etc. [1] this bit can only be set to logic 1 by su ccessful execution of the authent2 command [2] reading this bit always returns logic 0 2 idleirq 1 command terminates correctly. for example; when the command register changes its value from an y command to the idle command. if an unknown command is started the idleirq bit is set. microprocessor start-up of the idle command does not set the idleirq bit. 0 idleirq = logic 0 in all other instances 1 hialertirq 1 primarystatus register hialert bit is set [1] 0 primarystatus register hialert bit is not set 0 loalertirq 1 primarystatus re gister loalert bit is set [1] 0 primarystatus register loalert bit is not set table 48. interruptrq register bit descriptions ?continued bit symbol value description table 49. control register (address: 09h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 00 standby powerdown crypt o1on tstopnow tstartnow flushfifo access r/w d d d w w w table 50. control register bit descriptions bit symbol value description 7 to 6 00 - reserved 5 standby 1 activates standby mode. the current consuming blocks are switched off but the clock keeps running 4 powerdown 1 activates power-down mode. the current consuming blocks are switched off including the clock 3 crypto1on 1 crypto1 unit is switched on and all data communication with the card is encrypted [1] 0 crypto1 unit is switched off. all data communication with the card is unencrypted (plain) 2 tstopnow 1 immediately stops the timer [2] 1 tstartnow 1 immediately starts the timer [2] 0 flushfifo 1 immediately clears the internal fifo buffer?s read and write pointer, the fifolength[6:0] bits are set to logic 0 and the fifoovfl flag [2]
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 49 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.2.3 errorf lag register error flags show the error status of the last executed command. table 51. errorflag register (address: 0ah) reset value: 0100 0000b, 40h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0 keyerr accesserr fifoovfl crc err framingerr parityerr collerr access r r r r r r r r table 52. errorflag register bit descriptions bit symbol value description 7 0 - reserved 6 keyerr 1 set when the loadkeye2 or loa dkey command recognize that the input data is not encoded based on the key format definition 0 set when the loadkeye2 or the loadkey command starts 5 accesserr 1 set when the access rights to the eeprom are violated 0 set when an eeprom related command starts 4 fifoovfl 1 set when the microprocessor or mfrc500 internal state machine (e.g. receiver) tries to write data to the fifo buffer when it is full 3 crcerr 1 set when rxcrcen is set and the crc fails 0 automatically set during the preparerx state in the receiver start phase 2 framingerr 1 set when the sof is incorrect 0 automatically set during the preparerx state in the receiver start phase 1 parityerr 1 set when the parity check fails 0 automatically set during the preparerx state in the receiver start phase 0 collerr 1 set when a bit-collision is detected 0 automatically set during the preparerx state in the receiver start phase
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 50 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.2.4 collpos register bit position of the first bit-collision detected on the rf interface. 10.5.2.5 timervalue register value of the timer. 10.5.2.6 crcresultlsb register lsb of the crc coprocessor register. table 53. collpos register (address: 0bh) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol collpos[7:0] access r table 54. collpos register bit descriptions bit symbol description 7 to 0 collpos[7:0] this register shows the bit position of the first det ected collision in a received frame. example: 00h indicates a bit collision in the start bit 01h indicates a bit collision in the 1 st bit ... 08h indicates a bit collision in the 8 th bit table 55. timervalue register (address: 0ch) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol timervalue[7:0] access r table 56. timervalue register bit descriptions bit symbol description 7 to 0 timervalue[7:0] this register shows the timer counter value table 57. crcresultlsb register (address: 0dh) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol crcresultlsb[7:0] access r table 58. crcresultlsb regi ster bit descriptions bit symbol description 7 to 0 crcresultlsb[7:0] gives the crc register?s least significant byte value; only valid if crcready = logic 1
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 51 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.2.7 crcresultmsb register msb of the crc coprocessor register. 10.5.2.8 bitframing register adjustments for bit oriented frames. table 59. crcresultmsb register (address: 0eh) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol crcresultmsb[7:0] access r table 60. crcresultmsb register bit descriptions bit symbol description 7 to 0 crcresultmsb[7:0] gives the crc register?s most significant byte value; only valid if crcready = logic 1. the register?s value is undefined for 8-bit crc calculation. table 61. bitframing register (address: 0fh) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0 rxalign[2:0] 0 txlastbits[2:0] access r/w d r/w d table 62. bitframing register bit descriptions bit symbol value description 70 - reserved 6 to 4 rxalign[2:0] defines the bit position in the fifo buffer for the first bit received and stored. additional received bits are stored in the next subsequent bit positions. after reception, rxalign[2:0] is automatically cleared. for example: 000 the lsb of the received bit is stored in bit position 0 and the second received bit is stored in bit position 1 001 the lsb of the received bit is stored in bit position 1, the second received bit is stored in bit position 2 ... 111 the lsb of the received bit is stored in bit position 7, the second received bit is stored in the next byte in bit position 0 30 - reserved 2 to 0 txlastbits[2:0] - defines the number of bits of the last byte that shall be transmitted. 000 indicates that al l bits of the last byte will be transmitted. txlastbits[2:0] is automatically cleared after transmission.
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 52 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.3 page 2: transmitter and control 10.5.3.1 page register selects the page register; see section 10.5.1.1 ? page register ? on page 43 . 10.5.3.2 txcontrol register controls the logical behavior of the antenna pins tx1 and tx2. table 63. txcontrol register (address: 11h) reset value: 0101 1000b, 58h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0 modulatorsource[1:0] 1 tx2inv tx2cw tx2rfen tx1rfen access r/w r/w r/w r/w r/w r/w r/w table 64. txcontrol register bit descriptions bit symbol value description 7 0 - this value must not be changed 6 to 5 modulatorsource[1:0] selects the source for the modulator input: 00 modulator input is low 01 modulator input is high 10 modulator input is the internal encoder 11 modulator input is pin mfin 4 1 - this value must not be changed 3 tx2inv 1 delivers an inverted 13.56 mhz energy carrier output signal on pin tx2 2 tx2cw 1 delivers a continuously unmodulated 13.56 mhz energy carrier output signal on pin tx2 0 enables modulation of the 13.56 mhz energy carrier 1 tx2rfen 1 the output signal on pin tx2 is the 13.56 mhz energy carrier modulated by the transmission data 0 tx2 is driven at a constant output level 0 tx1rfen 1 the output signal on pin tx1 is the 13.56 mhz energy carrier modulated by the transmission data 0 tx1 is driven at a constant output level
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 53 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.3.3 cwconductance register selects the conductance of the antenna driver pins tx1 and tx2. see section 9.9.3.1 for detailed information about gscfgcw[5:0]. 10.5.3.4 preset13 register these bit settings must not be changed. 10.5.3.5 preset14 register these bit settings must not be changed. table 65. cwconductance register (address: 12h) reset value: 0011 1111b, 3fh bit allocation bit 7 6 5 4 3 2 1 0 symbol 00 gscfgcw[5:0] access r/w r/w table 66. cwconductance register bit descriptions bit symbol value description 7 to 6 00 0 these values must not be changed 5 to 0 gscfgcw[5:0] - defines the conductance register value for the output driver. this can be used to regulate the output power/current consumption and operating distance. table 67. preset13 register (address: 13h) reset value: 0011 1111b, 3fh bit allocation bit 7 6 5 4 3 2 1 0 symbol 00 11111 access r/w r/w table 68. preset13 register bit descriptions bit symbol value description 7 to 6 00 0 these values must not be changed 5 to 0 11111 - these values must not be changed table 69. preset14 register (address: 14h) reset value: 0001 1001b, 19h bit allocation bit 7 6 5 4 3 2 1 0 symbol 000 11 00 1 access r/w r/w r/w r/w table 70. preset14 register bit descriptions bit symbol value description 7 to 5 000 0 these values must not be changed 4 to 3 11 1 these values must not be changed 2 to 1 00 0 these values must not be changed 0 1 1 these values must not be changed
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 54 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.3.6 modwidth register selects the pulse-modulation width. 10.5.3.7 preset16 register these bit settings must not be changed. 10.5.3.8 preset17 register these bit settings must not be changed. table 71. modwidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation bit 7 6 5 4 3 2 1 0 symbol modwidth[7:0] access r/w table 72. modwidth register bit descriptions bit symbol description 7 to 0 modwidth[7:0] defines the width of the modulation pulse based on t mod =2 ? (modwidth + 1) / f clk table 73. preset16 register (address: 16h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 00000000 access r/w table 74. preset16 register bit descriptions bit symbol value description 7 to 0 00000000 0 these values must not be changed table 75. preset17 register (address: 17h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 00000000 access r/w table 76. preset17 register bit descriptions bit symbol value description 7 to 0 00000000 0 these values must not be changed
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 55 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.4 page 3: receiver and decoder control 10.5.4.1 page register selects the page register; see section 10.5.1.1 ? page register ? on page 43 . 10.5.4.2 rxcontrol1 register controls receiver operation. 10.5.4.3 decodercontrol register controls decoder operation. table 77. rxcontrol1 register (address: 19h) reset value: 0111 0011b, 73h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0 111 00 gain[1:0] access r/w r/w r/w r/w table 78. rxcontrol1 register bit descriptions bit symbol value description 7 0 0 these values must not be changed 6 to 4 111 1 these values must not be changed 3 to 2 00 0 these values must not be changed 1 to 0 gain[1:0] defines the receiver?s signal voltage gain factor 00 20 db gain factor 01 24 db gain factor 10 31 db gain factor 11 35 db gain factor table 79. decodercontrol register (addre ss: 1ah) reset value: 0000 1000b, 08h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0 rxmultiple zeroaftercoll 0 1 000 access r/w r/w r/w r/w r/w r/w table 80. decodercontrol register bit descriptions bit symbol value description 7 0 - this value must not be changed 6 rxmultiple 0 after receiving one fram e, the receiver is deactivated 1 enables reception of more than one frame 5 zeroaftercoll 1 any bits received after a bit-collision are masked to zero. this helps to resolve the anti-collision procedure as defined in iso/iec 14443 a 4 0 0 this value must not be changed 3 1 1 this value must not be changed 2 to 0 000 0 these values must not be changed
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 56 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.4.4 bitphase register selects the bit-phase between transmitter and receiver clock. 10.5.4.5 rxthreshold register selects thresholds for the bit decoder. 10.5.4.6 preset1d register these bit settings must not be changed. table 81. bitphase register (address: 1bh) reset value: 1010 1101b, adh bit allocation bit 7 6 5 4 3 2 1 0 symbol bitphase[7:0] access r/w table 82. bitphase register bit descriptions bit symbol description 7 to 0 bitphase[7:0] defines the phase relationship between transmitter and receiver clock remark: the correct value of this register is essential for proper operation. table 83. rxthreshold register (address: 1ch) reset value: 1111 1111b, ffh bit allocation bit 7 6 5 4 3 2 1 0 symbol minlevel[3:0] colllevel[3:0] access r/w r/w table 84. rxthreshold register bit descriptions bit symbol description 7 to 4 minlevel[3:0] the minimum signal str ength the decoder will ac cept. if the signal strength is below this level, it is not evaluated. 3 to 0 colllevel[3:0] the minimum signal streng th the decoder input that must be reached by the weaker half-bit of the manchester encoded signal to generate a bit-collision (relative to the am plitude of the stronger half-bit) table 85. preset1d register (address: 1dh) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 00000000 access r/w table 86. preset1d register bit descriptions bit symbol value description 7 to 0 00000000 0 these values must not be changed
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 57 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.4.7 rxcontrol2 register controls decoder behavior and defines the input source for the receiver. [1] i-clock and q-clock are 90 ? phase-shifted from each other. 10.5.4.8 clockqcontrol register controls clock generation for the 90 ? phase-shifted q-clock. table 87. rxcontrol2 register (address: 1eh) reset value: 0100 0001b, 41h bit allocation bit 7 6 5 4 3 2 1 0 symbol rcvclkseli rxautopd 0000 decodersource[1:0] access r/w r/w r/w r/w table 88. rxcontrol2 register bit descriptions bit symbol value description 7 rcvclkseli 1 i-clock is used as the receiver clock [1] 0 q-clock is used as the receiver clock [1] 6 rxautopd 1 receiver circuit is automatically switched on before receiving and switched off afterwards. this can be used to reduce current consumption. 0 receiver is always activated 5 to 2 0000 - these values must not be changed 1 to 0 decodersource[1:0] selects the source for the decoder input 00 low 01 internal demodulator 10 a subcarrier modulated manchester encoded signal on pin mfin 11 a baseband manchester encoded signal on pin mfin table 89. clockqcontrol register (address: 1f h) reset value: 000x xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol clkq180deg clkqcalib 0 clkqdelay[4:0] access r r/w r/w d table 90. clockqcontrol register bit descriptions bit symbol value description 7 clkq180deg 1 q-clock is phase-shifted more than 180 ? compared to the i-clock 0 q-clock is phase-sh ifted less than 180 ? compared to the i-clock 6 clkqcalib 0 q-clock is automatically calibrated after the reset phase and after data reception from the card 1 no calibration is performed automatically 5 0 - this value must not be changed 4 to 0 clkqdelay[4:0] - this register shows the number of delay elements used to generate a 90 ? phase-shift of the i-clock to obtain the q-clock. it can be written dire ctly by the microprocessor or by the automatic calibration cycle.
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 58 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.5 page 4: rf timing and channel redundancy 10.5.5.1 page register selects the page register; see section 10.5.1.1 ? page register ? on page 43 . 10.5.5.2 rxwait register selects the time interval after transmission, before the receiver starts. 10.5.5.3 channelredundancy register selects kind and mode of checking the data integrity on the rf channel. table 91. rxwait register (address: 21h) r eset value: 0000 0101b, 06h bit allocation bit 7 6 5 4 3 2 1 0 symbol rxwait[7:0] access r/w table 92. rxwait register bit descriptions bit symbol function 7 to 0 rxwait[7:0] after data transmission, t he activation of the receiver is delayed for rxwait bit-clock cycles. duri ng this frame guard time any signal on pin rx is ignored. table 93. channelredundancy register (addre ss: 22h) reset value: 0000 0011b, 03h bit allocation bit 7 6 5 4 3 2 1 0 symbol 00 crc3309 crc8 rxcrcen txcrcen parityodd parityen access r/w r/w r/w r/w r/w r/w r/w r/w table 94. channelredundancy bit descriptions bit symbol value function 7 to 6 00 - this value must not be changed 5 crc3309 1 crc calculation is performed using iso/iec 3309 and iso/iec 15693 0 crc calculation is performed using iso/iec 14443 a 4 crc8 1 an 8-bit crc is calculated 0 a 16-bit crc is calculated 3 rxcrcen 1 the last byte(s) of a received frame are interpreted as crc bytes. if the crc is correct, the crc bytes are not passed to the fifo. if the crc bytes are incorrect, the crcerr flag is set. 0 no crc is expected 2 txcrcen 1 a crc is calculated over the transmitted data and the crc bytes are appended to the data stream 0 no crc is transmitted
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 59 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution [1] with iso/iec 14443 a, this bit must be set to logic 1. 10.5.5.4 crcpresetlsb register lsb of the preset value for the crc register. 10.5.5.5 crcpresetmsb register msb of the preset value for the crc register. 10.5.5.6 preset25 register these values must not be changed. 1 parityodd 1 odd parity is generated or expected [1] 0 even parity is generated or expected 0 parityen 1 a parity bit is inserted in the transmitted data stream after each byte and expected in the received data stream after each byte (mifare, iso/iec 14443 a) 0 no parity bit is inserted or expected table 94. channelredundancy bit descriptions ?continued bit symbol value function table 95. crcpresetlsb register (address: 23h) reset value: 0101 0011b, 63h bit allocation bit 7 6 5 4 3 2 1 0 symbol crcpresetlsb[7:0] access r/w table 96. crcpresetlsb register bit descriptions bit symbol description 7 to 0 crcpresetlsb[7:0] defines the start val ue for crc calculation. this value is loaded into the crc at the beginning of transmission, reception and the calccrc command (if crc calculation is enabled). table 97. crcpresetmsb register (address: 24h) reset value: 0101 0011b, 63h bit allocation bit 7 6 5 4 3 2 1 0 symbol crcpresetmsb[7:0] access r/w table 98. crcpresetmsb bit descriptions bit symbol description 7 to 0 crcpresetmsb[7:0] defines the starting value for crc calculation. this value is loaded into the crc at the beginni ng of transmission, reception and the calccrc command (if the crc calculation is enabled) remark: this register is not relevant if crc8 is set to logic 1. table 99. preset25 register (address: 25h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 00000000 access r/w
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 60 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.5.7 mfoutselect register selects the internal signal applied to pin mfout. [1] only valid for mifare and iso/iec 14443 a communication at 106 kbd. 10.5.5.8 preset27 register table 100. preset25 register bit descriptions bit symbol value description 7 to 0 00000000 0 these values must not be changed table 101. mfoutselect register (address: 26 h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 00000 mfoutselect[2:0] access r/w r/w table 102. mfoutselect register bit descriptions bit symbol value description 7 to 3 00000 0 these values must not be changed 2 to 0 mfoutselect[2:0] defines which signal is routed to pin mfout: 000 constant low 001 constant high 010 modulation signal (envelope) from the internal encoder, (miller coded) 011 serial data stream, not miller encoded 100 output signal of the energy carrier demodulator (card modulation signal) [1] 101 output signal of the subcarrier demodulator (manchester encoded card signal) [1] 110 reserved 111 reserved table 103. preset27 (address: 27h) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access w table 104. preset27 register bit descriptions bit symbol value description 7 to 0 xxxxxxxx 0 these values c an be logic 1 or logic 0
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 61 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.6 page 5: fifo, timer and irq pin configuration 10.5.6.1 page register selects the page register; see section 10.5.1.1 ? page register ? on page 43 . 10.5.6.2 fifolevel register defines the levels for fifo underflow and overflow warning. 10.5.6.3 timerclock register selects the divider for the timer clock. table 105. fifolevel register (address: 29h) r eset value: 0000 1000b, 08h bit allocation bit 7 6 5 4 3 2 1 0 symbol 00 waterlevel[5:0] access r/w r/w table 106. fifolevel register bit descriptions bit symbol description 7 to 6 00 these values must not be changed 5 to 0 waterlevel[5:0] defines, the warning leve l of a fifo buffer overflow or underflow: hialert is set to logic 1 if the remaining fifo buffer space is equal to, or less than, waterlevel[5:0] bits in the fifo buffer. loalert is set to logic 1 if equal to, or less than, waterlevel[5:0] bits in the fifo buffer. table 107. timerclock register (address: 2ah) reset value: 0000 0111b, 07h bit allocation bit 7 6 5 4 3 2 1 0 symbol 00 tautorestart tprescaler[4:0] access rw rw rw table 108. timerclock register bit descriptions bit symbol value function 7 to 6 00 0 these values must not be changed 5 tautorestart 1 the timer automatically restarts its countdown from the treloadvalue[7:0] instead of counting down to zero 0 the timer decrements to zero and register interruptirq timerirq bit is set to logic 1 4 to 0 tprescaler[4:0] - defines the timer clock frequency (f timerclock ). the tprescaler[4:0] can be adjusted from 0 to 21. the following formula is used to calculate the timerclock frequency (f timerclock ): f timerclock = 13.56 mhz / 2 tprescaler [mhz]
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 62 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.6.4 timercontrol register selects start and stop conditions for the timer. 10.5.6.5 timerreload register defines the preset value for the timer. table 109. timercontrol register (address: 2bh) reset value: 0000 0110b, 06h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0000 tstoprxend tstoprxbegin tstarttxend tstarttxbegin access r/w r/w r/w r/w r/w table 110. timercontrol register bit descriptions bit symbol value description 7 to 4 0000 0 these values must not be changed 3 tstoprxend 1 the timer automatically stops when data reception ends 0 the timer is not influenced by this condition 2 tstoprxbegin 1 the timer autom atically stops when the first valid bit is received 0 the timer is not influenced by this condition 1 tstarttxend 1 the timer automatically st arts when data transmission ends. if the timer is already running, the timer restarts by loading treloadvalue[7:0] into the timer. 0 the timer is not influenced by this condition 0 tstarttxbegin 1 the timer automatically starts when the first bit is transmitted. if the timer is already running, the timer restarts by loading treloadvalue[7:0] into the timer. 0 the timer is not influenced by this condition table 111. timerreload register (address: 2ch) reset value: 0000 1010b, 0ah bit allocation bit 7 6 5 4 3 2 1 0 symbol treloadvalue[7:0] access r/w table 112. timerreload register bit descriptions bit symbol description 7 to 0 treloadvalue[7:0] on a start event, th e timer loads the treloadvalue[7:0] value. changing this register only affects the timer on the next start event. if treloadvalue[7:0] is set to logic 0 the timer cannot start.
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 63 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.6.6 irqpinconfig register configures the output stage for pin irq. 10.5.6.7 preset2e register 10.5.6.8 preset2f register 10.5.7 page 6: reserved 10.5.7.1 page register selects the page register; see section 10.5.1.1 ? page register ? on page 43 . 10.5.7.2 reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h remark: these registers are reserved for future use. table 113. irqpinconfig register (address: 2dh) reset value: 0000 0010b, 02h bit allocation bit 7 6 5 4 3 2 1 0 symbol 000000 irqinv irqpushpull access r/w r/w r/w table 114. irqpinconfig register bit descriptions bit symbol value description 7 to 2 000000 0 these values must not be changed 1 irqinv 1 inverts the signal on pin irq with respect to bit irq 0 the signal on pin irq is not inverted and is the same as bit irq 0 irqpushpull 1 pin irq functions as a standard cmos output pad 0 pin irq functions as an open-drain output pad table 115. preset2e register (address: 2eh) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access w table 116. preset2f register (address: 2fh) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access w table 117. reserved registers (address: 31h, 32h, 33h, 34h, 35h, 36h, 37h) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access w
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 64 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.8 page 7: test control 10.5.8.1 page register selects the page register; see section 10.5.1.1 ? page register ? on page 43 . 10.5.8.2 reserved register 39h remark: this register is reserved for future use. 10.5.8.3 testanaselect register selects analog test signals. table 118. reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access w table 119. testanaselect register (address: 3a h) reset value: 0000 0000b, 00h bit allocation bit 7 6 5 4 3 2 1 0 symbol 0000 testanaoutsel[4:0] access w w table 120. testanaselect bit descriptions bit symbol value description 7 to 4 0000 0 these values must not be changed 3 to 0 testanaoutsel[4:0] selects the internal analog signal to be routed to the aux pin. see section 15.2.2 on page 96 for detailed information. the settings are as follows: 0vmid 1 vbandgap 2 vrxfolli 3 vrxfollq 4vrxampi 5vrxampq 6 vcorrni 7 vcorrnq 8 vcorrdi 9 vcorrdq a vevall b vevalr cvtemp d reserved e reserved f reserved
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 65 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.8.4 reserved register 3bh remark: this register is reserved for future use. 10.5.8.5 reserved register 3ch remark: this register is reserved for future use. 10.5.8.6 testdigiselect register selects digital test mode. table 121. reserved register (address: 3bh) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access w table 122. reserved register (address: 3ch) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access w table 123. testdigiselect register (address: 3d h) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol signaltomfout testdigisignalsel[6:0] access w w table 124. testdigiselect register bit descriptions bit symbol value description 7 signaltomfout 1 overrules the mfouts elect[2:0] setting and routes the digital test signal defined with the testdigisignalsel[6:0] bits to pin mfout 0 mfoutselect[2:0] defines the signal on pin mfout 6 to 0 testdigisignalsel[6:0] - selects the digita l test signal to be routed to pin mfout. refer to section 15.2.3 on page 97 for detailed information. the following lists the signal names for the testdigisignalsel[6:0] addresses: f4h s_data e4h s_valid d4h s_coll c4h s_clock b5h rd_sync a5h wr_sync 96h int_clock
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 66 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 10.5.8.7 reserved registers 3eh, 3fh remark: this register is reserved for future use. 11. mfrc500 command set mfrc500 operation is determined by an internal state machine capable of performing a command set. the commands can be started by writing the command code to the command register. arguments and/or data necessary to process a command are mainly exchanged using the fifo buffer. ? each command needing a data stream (or data byte stream) as an input immediately processes the data in the fifo buffer ? each command that requires arguments only starts processing when it has received the correct number of arguments from the fifo buffer ? the fifo buffer is not automatically cleared at the start of a command. it is, therefore, possible to write command arguments and/or the data bytes into the fifo buffer before starting a command. ? each command (except the startup command) can be interrupted by the microprocessor writing a new command code to the command register e.g. the idle command. 11.1 mfrc500 command overview table 125. reserved register (address: 3eh, 3fh) reset value: xxxx xxxxb, xxh bit allocation bit 7 6 5 4 3 2 1 0 symbol xxxxxxxx access w table 126. mfrc500 commands overview command value action fifo communication arguments and data sent data received startup 3fh runs the reset and initialization phase. see section 11.1.2 on page 68 . remark: this command can only be activated by power-on or hard resets. -- idle 00h no action; cancels exec ution of the current command. see section 11.1.3 on page 68 -- transmit 1ah transmits data from the fifo buffer to the card. see section 11.2.1 on page 69 data stream - receive 16h activates receiver circui try. before the receiver starts, the state machine waits until the time defined in the rxwait register has elapsed. see section 11.2.2 on page 72 . remark: this command may be used for test purposes only, since there is no timing relationship to the transmit command. - data stream
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 67 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution [1] this command is the combination of the transmit and receive commands. transceive [1] 1eh transmits data from fifo buffer to the card and automatically activates the receiver after transmission. the receiver waits until the time defined in the rxwait register has elapsed before starting. see section 11.2.3 on page 75 . data stream data stream writee2 01h reads data from the fifo buffer and writes it to the eeprom. see section 11.3.1 on page 77 . start address lsb - start address msb data byte stream reade2 03h reads data from the eeprom and sends it to the fifo buffer. see section 11.3.2 on page 79 . remark: keys cannot be read back start address lsb data bytes start address msb number of data bytes loadkeye2 0bh copies a key from the eeprom into the key buffer see section 11.6.1 on page 81 . start address lsb - start address msb loadkey 19h reads a key from the fifo buffer and loads it into the key buffer. see section 11.6.2 on page 81 . remark: the key has to be prepared in a specific format (refer to section 9.2.3.1 ? key format ? on page 13 ) byte 0 lsb - byte 1 ? byte 10 byte 11 msb authent1 0ch performs the first part of card authentication using the crypto1 algorithm. see section 11.6.3 on page 82 . card authent1 command - card block address card serial number lsb card serial number byte 1 card serial number byte 2 card serial number msb authent2 14h performs the second part of card authentication using the crypto1 algorithm. see section 11.6.4 on page 82 . -- loadconfig 07h r eads data from eeprom and initializes the mfrc500 registers. see section 11.4.1 on page 79 . start address lsb - start address msb calccrc 12h activates the crc coprocessor remark: the result of the crc calculation is read from the crcresultlsb and crcresultmsb registers. see section 11.4.2 on page 80 . data byte stream - table 126. mfrc500 commands overview ?continued command value action fifo communication arguments and data sent data received
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 68 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 11.1.1 basic states 11.1.2 startup command 3fh remark: this command can only be activated by a power-on or hard reset. the startup command runs the reset and initialization phases. it does not need or return, any data. it cannot be activated by the micr oprocessor but is automatically started after one of the following events: ? power-on reset (por) caused by power-up on pin dvdd or on pin avdd ? negative edge on pin rstpd the reset phase comprises an asynchronous reset and configuration of certain register bits. the initialization phase configures se veral registers with values stored in the eeprom. when the startup command finishes, the idle command is automatically executed. remark: ? the microprocessor must not write to th e mfrc500 while it is still executing the startup command. to avoid this, the microprocessor polls for the idle command to determine when the initialization phase has finished; see section 9.7.4 on page 25 . ? when the startup command is active, it is only possible to read from the page 0 register. ? the startup command cannot be interrupted by the microprocessor. 11.1.3 idle command 00h the idle command switches the mfrc500 to its inactive state where it waits for the next command. it does not need or return, any data. the device automatically enters the idle state when a command finishes. when this happens, the mfrc500 sends an interrupt request by setting bit idleirq. when triggered by the microprocessor, the idle command can be used to stop execution of all other commands (except the startup command) but this does not generate an interrupt request (idleirq). remark: stopping command execution with the idle command does not clear the fifo buffer. table 127. startup command 3fh command value action arguments and data returned data startup 3fh runs the reset and initialization phase - - table 128. idle command 00h command value action arguments and data returned data idle 00h no action; cancels current command execution --
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 69 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 11.2 commands for card communication the mfrc500 is a fully iso/iec 14443 a compliant reader ic. this enables the command set to be more flexible and generalized when compared to dedicated mifare reader ics. section 11.2.1 to section 11.2.5 describe the command set for iso/iec 14443 a card communication and related communication protocols. 11.2.1 transmit command 1ah the transmit command reads data from the fifo buffer and sends it to the transmitter. it does not return any data. the transmit command can only be started by the microprocessor. 11.2.1.1 using the transmit command to transmit data, one of the following sequences can be used: 1. all data to be transmitted to the card is written to the fifo buffer while the idle command is active. then the command code for the transmit command is written to the command register. remark: this is possible for tr ansmission of a data stream up to 64 bytes. 2. the command code for the transmit command is stored in the command register. since there is not any data available in t he fifo buffer, the command is only enabled but transmission is not activated. data tran smission starts when the first data byte is written to the fifo buffer. to generate a continuous data stream on the rf interface, the microprocessor must write the subsequent data bytes into the fifo buffer in time. remark: this allows transmission of any data st ream length but it requires data to be written to the fifo buffer in time. 3. part of the data transmitted to the card is written to the fifo buffer while the idle command is active. then the command code for the transmit command is written to the command register. while the transmit command is active, the microprocessor can send further data to the fifo buffer. this is then appended by the transmitter to the transmitted data stream. remark: this allows transmission of any data st ream length but it requires data to be written to the fifo buffer in time. when the transmitter requests the next data byte to ensure the data stream on the rf interface is continuous and th e fifo buffer is empty, the transmit command automatically exits. this causes the internal state machine to change its state from transmit to idle. when the data transmission to the card is fini shed, the txirq flag is set by the mfrc500 to indicate to the microprocess or transmission is complete. remark: if the microprocessor overwrites the transmit code in the command register with another command, transmission stops immedi ately on the next clock cycle. this can produce output signals that are not in accordance with iso/iec 14443 a. table 129. transmit command 1ah command value action arguments and data returned data transmit 1ah transmits data from fifo buffer to card data stream -
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 70 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 11.2.1.2 rf channel redundancy and framing each iso/iec 14443 a frame transmitted consis ts of a start of frame (sof) pattern, followed by the data stream and is closed by an end of frame (eof) pattern. these different phases of the transmission sequence can be monitored using the primarystatus register modemstate[2:0] bits; see section 11.2.4 on page 75 . depending on the setting of the channelredu ndancy register bit txcrcen, the crc is calculated and appended to the data stream. the crc is calculated according to the settings in the channelredundancy register. pari ty generation is handled according to the channelredundancy register parityen and parityodd bits settings. 11.2.1.3 transmission of bit oriented frames the transmitter can be configured to send an incomplete last byte. to achieve this the bitframing register?s txlastbits[2:0] bits must be set at above zero (for example, 1). this is shown in figure 14 . figure 14 shows the data stream when bit parityen is set in the channelredundancy register. all fully transmitted bytes are followe d by a parity check bi t but the incomplete byte is not followed by a parity check bit. after transmission, the txlastbits[2:0] bits are automatically cleared. remark: if the txlastbits[2:0] bits are not equal to zero, crc generation must be disabled. this is done by clearing the channelredundancy register txcrcen bit. 11.2.1.4 transmission of frames with more than 64 bytes to generate frames of more than 64 bytes, the microprocessor must write data to the fifo buffer while the transmit command is active. the state machine checks the fifo buffer status when it starts transmitting the la st bit of the data stream; the check time is shown in figure 15 with arrows. fig 14. transmitting bit oriented frames 001aak618 txlastbits = 0 txlastbits = 7 txlastbits = 1 0 7 p 0 7 p sof sof sof eof eof eof 0 7 p 0 6 0 7 p 0
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 71 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution as long as the internal signal accept further data is logic 1, data can be written to the fifo buffer. the mfrc500 appends this data to the data stream transmitted using the rf interface. if the internal accept further data signal is lo gic 0, the transmission terminates. all data written to the fifo buffer after the accept further data signal was set to logic 0 is not transmitted, however, it remains in the fifo buffer. remark: if parity generation is enabled (parityen = logic 1), the parity bit is the last bit transmitted. this delays the accept furthe r data signal by a duration of one bit. if the txlastbits[2:0] bits are not zero, the last byte is not transmitted completely. only the number of bits set by txlastbits[2:0], starting with the least significant bit are transmitted. this means that the internal state machine ha s to check the fifo buffer status at an earlier point in time; see figure 16 . since in this example txlastbits[2:0] = 4, transmission stops after bit 3 is transmitted and the frame is completed with an eof, if configured. fig 15. timing for transmitting byte oriented frames fig 16. timing for transmi tting bit oriented frames 001aak619 accept further data check fifo empty txdata fifo empty fifolength[6:0] 01h 00h txlastbits[2:0] txlastbits = 0 7 0 7 70 001aak620 accept further data check fifo empty txdata fifo empty fifolength[6:0] 01h 00h 01h 00h txlastbits[2:0] txlastbits = 4 nwr (fifo data) 7 0 3 4 7 0 3 4
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 72 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution figure 16 also shows write access to the fifodata register just before the fifo buffer?s status is checked. this leads to fifo empty state being held low which keeps the accept further data active. the new byte written to the fifo buffer is transmitted using the rf interface. accept further data is only changed by th e check fifo empty function. this function verifies fifo empty for one bit duration before the last expected bit transmission. 11.2.2 receive command 16h the receive command activates the receiver circuitry. all data received from the rf interface is written to the fifo buffer. the receive command can be started either using the microprocessor or automatically during execution of the transceive command. remark: this command can only be used for test purposes since there is no timing relationship to the transmit command. 11.2.2.1 using the receive command after starting the receive command, the internal state machine decrements to the rxwait register value on every bit-clock. the analog receiver circuitry is prepared and activated from 3 down to 1. when the counter reaches 0, the receiver starts monitoring the incoming signal at the rf interface. when the signal strength reaches a level higher than the rxthreshold register minlevel[3:0] bits value, it starts decoding. the decoder stops when the signal can longer be detected on the receiver input pin rx. th e decoder sets bit rxirq indicating receive termination. the different phases of the receive sequen ce are monitored using the primarystatus register modemstate[2:0] bits; see section 11.2.4 on page 75 . remark: since the counter values from 3 to 0 are needed to initialize the analog receiver circuitry, the minimum value for rxwait[7:0] is 3. table 130. transmission of frames of more than 64 bytes frame definition verification at: 8-bit with parity 8 th bit 8-bit without parity 7 th bit x-bit without parity (x ? 1) th bit table 131. receive command 16h command value action arguments and data returned data receive 16h activates receiver circuitry - data stream
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 73 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 11.2.2.2 rf channel redundancy and framing the decoder expects the sof pattern at the beginning of each data stream. when the sof is detected, it activates the serial-to-parallel converter and gathers the incoming data bits. every completed byte is forwarded to the fifo buffer. if an eof pattern is detected or the signal strength falls below the rxthreshold register minlevel[3:0] bits setting, both the receiver and the decoder stop. then the idle command is entered and an appropriate response for the microprocessor is generated (interrupt request activated, status flags set). when the channelredundancy r egister bit rxcrcen is set, a crc block is expected. the crc block can be one byte or two bytes depending on the channelredundancy register crc8 bit setting. remark: if the crc block received is correct, it is not sent to the fifo buffer. this is realized by shifting the incoming data bytes through an internal buffer of either one or two bytes (depending on the defined crc). the crc block remains in this internal buffer. consequently, all data bytes in the fifo buffer are delayed by one or two bytes. if the crc fails, all received bytes are sent to the fifo buffer including the faulty crc. if parityen is set in the channelredundancy re gister, a parity bit is expected after each byte. if parityodd = logic 1, the expected parity is odd, otherwise even parity is expected. 11.2.2.3 collision detection if more than one card is within the rf field during the card selection phase, they both respond simultaneously. the mfrc500 supports the algorithm defined in iso/iec 14443 a to resolve card serial nu mber data collisions by performing the anti-collision proced ure. the basis for this procedure is the ability to detect bit-collisions. bit-collision detection is supp orted by the ma nchester coding bit en coding scheme used in the mfrc500. if in the first and second half-b it of a subcarrier, modulation is detected, instead of forwarding a 1-bit or 0-bit, a bit- collision is indicated. the mfrc500 uses the rxthreshold register colllevel[3 :0] bits setting to distinguish between a 1-bit or 0-bit and a bit-collision. if the amplitud e of the half-bit with smaller am plitude is larger than that defined by the colllevel[3:0] bits, the mfrc 500 flags a bit-collisi on using the error flag collerr. if a bit-collision is detected in a parity bit, the parityerr flag is set. on a detected collision, the receiver continue s receiving the incoming data stream. in the case of a bit-collision, the decoder sends logic 1 at the collision position. remark: as an exception, if bit zeroaftercoll is set, all bits received after the first bit-collision are forced to zero , regardless whether a bit-collis ion or an unequivocal state has been detected. this feature makes it eas ier for the control software to perform the anti-collision proced ure as defined in iso/iec 14443 a. when the first bit collision in a frame is detect ed, the bit-collision posi tion is stored in the collpos register. table 132 shows the collision positions.
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 74 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution parity bits are not counted in the collpos register because bit- collisions in parity bit occur after bit-collisions in the data bits. if a collisio n is detected in the sof, a frame error is flagged and no data is sent to the fifo buff er. in this case, the receiver continues to monitor the incoming signal. it generates t he correct notifications to the microprocessor when the end of the faulty input stream is detected. this helps the microprocessor to determine when it is next allowed to send data to the card. 11.2.2.4 receiving bit oriented frames the receiver can manage byte streams with inco mplete bytes which result in bit-oriented frames. to support this, the following values may be used: ? bitframing register?s rxalign[2:0] bits select a bit offset for the first incoming byte. for example, if rxalign[2:0] = 3, the first 5 bits received are forwarded to the fifo buffer. further bits are packed into bytes and forwarded. after reception, rxalign[2:0] is automatically cleared. if rxalign[2:0] = logic 0, all incoming bits are packed into one byte. ? rxlastbits[2:0] returns the number of bits va lid in the last received byte. for example, if rxlastbits[2:0] evaluates to 5 bits at the end of the received command, the 5 least significant bits are valid. if the last byte is complete, rxlastbits[2 :0] evaluates to zero. rxlastbits[2:0] is only valid if a frame error is not indicated by the framingerr flag. if rxalign[2:0] is not zero and parityen is ac tive, the first parity bit is ignored and not checked. the first byte containing a single bit from the card is not sent to the microprocessor but suppressed when if rxalign[2:0] is set to 7 (see section 10.5.2.4 on page 50 ). remark: collisions detected at collpos register bit positions 6, 14, 22, 30 and 38 cannot be resolved using rxalign[2:0]. they must be resolved using the control software. 11.2.2.5 communi cation errors the events which can set error flags are shown in table 133 . table 132. return values for bit-collision positions collision in bit collpos register value (decimal) sof 0 least significant bit (lsb) of the least significant byte (lsbyte) 1 ?? most significant bit (msb) of the lsbyte 8 lsb of second byte 9 ?? msb of second byte 16 lsb of third byte 17 ??
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 75 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 11.2.3 transceive command 1eh the transceive command first exec utes the transmit command (see section 11.2.1 on page 69 ) and then starts the receive command (see section 11.2.2 on page 72 ). all data transmitted is sent using the fifo buffer and all data received is written to the fifo buffer. the transceive command can only be started by the microprocessor. remark: to adjust the timing relationship betw een transmitting and receiving, use the rxwait register. this register is used to define the time delay between the last bit transmitted and activation of the receiver. in addition, the bitphase register determines the phase-shift between the transmitter and receiver clock. 11.2.4 card communication states the status of the transmitter and receiver state machine can be read from bits modemstate[2:0] in the primarystatus register. the assignment of modemstate[2:0] to the internal action is shown in ta b l e 1 3 5 . table 133. communication error table cause flag bit received data did not start with the sof pattern framingerr crc block is not equal to the expected value crcerr received data is shorter than the crc block crcerr the parity bit is not equal to the expected va lue (i.e. a bit-collision, not parity) parityerr a bit-collision is detected collerr table 134. transceive command 1eh command value action arguments and data returned data transceive 1eh transmits data from fifo buffer to the card and then automatically activates the receiver data stream data stream table 135. meaning of modemstate modemstate [2:0] state description 000 idle transmitter and/or re ceiver are not operating 001 txsof transmitting the sof pattern 010 txdata transmitting data or redundancy check (crc) bits from the fifo buffer 011 txeof transmitting the eof pattern 100 gotorx1 intermediate state passed, when receiver starts gotorx2 intermediate state passed, when receiver finishes 101 preparerx waiting until the rxwa it register time period expires 110 awaitingrx receiver activated; wa iting for an input signal on pin rx 111 receiving receiving data
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 76 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 11.2.5 card communication state diagram fig 17. card communication state diagram 001aak621 end of receive frame and rxmultiple = 0 rxmultiple = 1 eof transmitted and command = transceive fifo not empty and command = transmit or transceive command = receive command = transmit, receive or transceive set command register = idle (000) awaiting rx (110) receiving (111) gotorx2 (100) prepare rx (101) gotorx1 (100) txeof (011) txdata (010) txsof (001) idle (000) sof transmitted next bit clock data transmitted rxwaitc[7:0] = 0 eof transmitted and command = transmit signal strength > minlevel[3:0] frame received
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 77 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 11.3 eeprom commands 11.3.1 writee2 command 01h the writee2 command interprets the first tw o bytes in the fifo buffer as the eeprom start byte address. any further bytes are interpreted as data bytes and are programmed into the eeprom, starting fr om the given eeprom start by te address. this command does not return any data. the writee2 command can onl y be started by the micr oprocessor. it will not stop automatically but has to be stopped explicitly by the microprocessor by issuing the idle command. 11.3.1.1 programming process one byte up to 16 bytes can be programmed into the eeprom during a single programming cycle. the time n eeded is approximately 5.8 ms. the state machine copies all the prepared data bytes to the fifo buffer and then to the eeprom input buffer. the internal eeprom inpu t buffer is 16 bytes long which is equal to the block size of the eeprom. a programming cycle is st arted if the last position of the eeprom input buffer is written or if the last byte of the fifo buffer has been read. the e2ready flag remains logic 0 when there are unprocessed bytes in the fifo buffer or the eeprom programming cycle is still in pr ogress. when all the data from the fifo buffer are programmed into the eeprom, the e2ready flag is set to logic 1. together with the rising edge of e2ready the txirq interrupt request flag shows logic 1. this can be used to generate an interrupt when programming of all data is finished. once e2ready = logic 1, the writee2 command can be stopped by the microprocessor by sending the idle command. remark: during the eeprom programmi ng indicated by e2ready = logic 0, the writee2 command cannot be stopped using any other command. table 136. writee2 command 01h command value action fifo arguments and data returned data writee2 01h get data from fi fo buffer and write it to the eeprom start address lsb - start address msb - data byte stream -
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 78 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 11.3.1.2 timing diagram figure 18 shows programming five bytes into the eeprom. assuming that the mfrc500 finds and reads byte 0 before the microprocessor is able to write byte 1 (t prog,del = 300 ns). this causes the mfrc500 to start the programming cycle (t prog ), which takes approximately 5.8 ms to complete. in the meantime, the microprocessor stores byte 1 to byte 4 in the fifo buffer. if the eeprom start byte address is 16ch then byte 0 is stored at that address. the mfrc500 copies the subsequ ent data bytes into the eeprom input buffer. whilst copying byte 3, it detects that this data byte has to be programmed at the eeprom byte address 16fh. as this is the end of the memory block, the mfrc500 automatically starts a programming cycle. next, byte 4 is programmed at the eeprom byte address 170h. as this is the last data byte, the e2ready and txir q flags are set indicati ng the end of the eeprom programming activity. although all data has been programmed into the eeprom, the mfrc500 stays in the writee2 command. writing more data to the fifo buffer would l ead to another eeprom programming cycle continuing from eepro m byte address 171h. the command is stopped using the idle command. 11.3.1.3 writee2 command error flags programming is restricted for eeprom block 0 (eeprom byte address 00h to 0fh). if you program these addresses, the accesserr flag is set and a programming cycle is not started. addresses above 1ffh are taken modulo 200h; see section 9.2 on page 10 for the eeprom memory organization. fig 18. eeprom programm ing timing diagram 001aak623 nwr data writee2 command active eeprom programming e2ready txirq write e2 addr lsb addr msb byte 0 byte 1 t prog,del byte 2 byte 3 byte 4 programming byte 0 t prog programming byte 1, byte 2 and byte 3 t prog programming byte 4 t prog idle command
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 79 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 11.3.2 reade2 command 03h the reade2 command interprets the first two bytes stored in the fifo buffer as the eeprom starting byte address . the next byte specifies the number of data bytes returned. when all three argument bytes are available in the fifo buffer, the specified number of data bytes is copied from the eeprom into the fifo buffer, starting from the given eeprom starting byte address. the reade2 command can only be triggered by the microprocessor and it automatically stops when all data has been copied. 11.3.2.1 reade2 command error flags reading is restricted to eeprom blocks 8h to 1fh (key memory area). reading from these addresses sets th e flag accesserr = logic 1. addresses above 1ffh are taken as modulo 200h; see section 9.2 on page 10 for the eeprom memory organization. 11.4 diverse commands 11.4.1 loadconfig command 07h the loadconfig command interprets the first two bytes found in the fifo buffer as the eeprom starting byte address. when the two argument bytes are available in the fifo buffer, 32 bytes from the eeprom are copied into the control and other relevant registers, starting at the eeprom starting byte address. the loadconfig command can only be started by the microprocessor an d it automatically stops when all relevant registers have been copied. 11.4.1.1 register assignment the 32 bytes of eeprom content are written to the mfrc500 registers 10h to register 2fh; see section 9.2 on page 10 for the eeprom memory organization. remark: the procedure for the register assignment is the same as it is for the startup initialization (see section 9.7.3 on page 25 ). the difference is, the eeprom starting byte address for the startup initialization is fixed to 10h (block 1, byte 0). however, it can be chosen with the loadconfig command. table 137. reade2 command 03h command value action arguments returned data reade2 03h reads eeprom data and stores it in the fifo buffer start address lsb data bytes start address msb number of data bytes table 138. loadconfig command 07h command value action arguments and data returned data loadconfig 07h reads data from eeprom and initializes the registers start address lsb - start address msb -
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 80 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 11.4.1.2 relevant loadconfig command error flags valid eeprom starting byte addr esses are between 10h and 60h. copying from block 8h to 1fh (keys) is rest ricted. reading from t hese addresses sets the flag accesserr = logic 1. addresses above 1ffh are taken as modulo 200h; see section 9.2 on page 10 for the eeprom memory organization. 11.4.2 calccrc command 12h the calccrc command takes all the data from the fifo buffer as the input bytes for the crc coprocessor. all data stored in the fifo buffer before the command is started is processed. this command does not return any data to th e fifo buffer but the content of the crc can be read using the crcresultlsb and crcresultmsb registers. the calccrc command can only be started by the microprocessor and it does not automatically stop. it must be stopped by th e microprocessor sending the idle command. if the fifo buffer is empty, the calccrc command waits for further input before proceeding. 11.4.2.1 crc coprocessor settings table 140 shows the parameters that can be configured for the crc coprocessor. the crc polynomial for the 8-bit crc is fixed to x 8 + x 4 + x 3 + x 2 + 1. the crc polynomial for the 16-bit crc is fixed to x 16 + x 12 + x 5 + 1. 11.4.2.2 crc coprocessor status flags the crcready status flag indicates that th e crc coprocessor has finished processing all the data bytes in the fifo buffer. when the crcready flag is set to logic 1, an interrupt is requested which sets the txirq flag. this supports interrupt driven use of the crc coprocessor. when crcready and txirq flags are set to logic 1 the content of the crcresultlsb and crcresultmsb registers and the crcerr flag are valid. the crcresultlsb and crcresultmsb registers hold the content of the crc, the crcerr flag indicates crc validity for the processed data. table 139. calccrc command 12h command value action arguments and data returned data calccrc 12h activates the crc copr ocessor data byte stream - table 140. crc coprocessor parameters parameter value bit register crc register length 8-bit or 16-bit crc crc8 channelredundancy crc algorithm iso/iec 14443 a or iso/iec 3309 crc3309 channelredundancy crc preset value any crcpresetlsb crcpresetlsb crcpresetmsb crcpresetmsb
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 81 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 11.5 error handling during command execution if an error is detected during command execution, the primarystatus register err flag is set. the microprocessor can evaluate the status flags in the errorflag register to get information about the cause of the error. 11.6 mifare security commands 11.6.1 loadkeye2 command 0bh the loadkeye2 command interprets the first two bytes found in the fifo buffer as the eeprom starting byte address. the eeprom by tes starting from t he given starting byte address are interpreted as the key when stored in the correct key format as described in section 9.2.3.1 ? key format ? on page 13 . when both argument bytes are available in the fifo buffer, the command executes. the loadkeye2 command can only be started by the microprocessor and it automatically stops after copying the key from the eeprom to the key buffer. 11.6.1.1 relevant loadkeye2 command error flags if the key format is incorrect (see section 9.2.3.1 ? key format ? on page 13 ) an undefined value is copied into the key buffer and the keyerr flag is set. 11.6.2 loadkey command 19h table 141. errorflag register error flags overview error flag related commands keyerr loadkeye2, loadkey accesserr writee2, reade2, loadconfig fifoovlf no specific commands crcerr receive, transceive, calccrc framingerr receive, transceive parityerr receive, transceive collerr receive, transceive table 142. loadkeye2 command 0bh command value action arguments and data returned data loadkeye2 0bh reads a key from the eeprom and puts it into the internal key buffer start address lsb - start address msb - table 143. loadkey command 19h command value action arguments and data returned data loadkey 19h reads a key from the fifo buffer and puts it into the key buffer byte 0 (lsb) - byte 1 - ?- byte 10 - byte 11 (msb) -
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 82 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution the loadkey command interprets the first twelve bytes it finds in the fifo buffer as the key when stored in the correct key format as described in section 9.2.3.1 ? key format ? on page 13 . when the twelve argument bytes are available in the fifo buffer they are checked and, if valid, are copied into the key buffer. the loadkey command can only be started by the microprocessor and it automatically stops after copying the key from the fifo buffer to the key buffer. 11.6.2.1 relevant loadkey command error flags all bytes requested are copied from the fifo buffer to the key buffer. if the key format is not correct (see section 9.2.3.1 ? key format ? on page 13 ) an undefined value is copied into the key buffer and the keyerr flag is set. 11.6.3 authent1 command 0ch the authent1 command is a special transceiv e command; it sends six argument bytes to the card. the card?s response is not sent to the microprocessor, it is used instead to authenticate the card to the mfrc500 and vice versa. the authent1 command can be triggered only by the microprocessor. the sequence of states for this command are the same as those for the transceive command; see section 11.2.3 on page 75 . 11.6.4 authent2 command 14h the authent2 command is a special transcei ve command. it does not need an argument byte, however all the data needed to be sent to the card is assembled by the mfrc500. the card response is not sent to the microproce ssor but is used to authenticate the card to the mfrc500 and vice versa. the authent2 command can only be started by the microprocessor. the sequence of states for this command are the same as those for the transceive command; see section 11.2.3 on page 75 . table 144. authent1 command 0ch command value action arguments and data returned data authent1 0ch performs the first part of the crypto1 card authentication card authent1 command - card block address - card serial number lsb - card serial number byte1 - card serial number byte2 - card serial number msb - table 145. authent2 command 14h command value action arguments and data returned data authent2 14h performs the second part of the card authentication using th e crypto1 algorithm --
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 83 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 11.6.4.1 authent2 command effects if the authent2 command is successful, the au thenticity of card and the mfrc500 are proved. this automatically sets the crypto1o n control bit. when bit crypto1on = logic 1, all further card communication is encrypted using the crypto1 security algorithm. if the authent2 command fails, bit crypto1on is cleared (crypto1on = logic 0). remark: the crypto1on flag can only be set by a successfully executed authent2 command and not by the microprocessor. the microprocessor can clear bit crypto1on to continue with unencrypted (plain) card communication. remark: the authent2 command must be executed immediately after a successful authent1 command; see section 11.6.3 ? authent1 command 0ch ? . in addition, the keys stored in the key buffer and those on the card must match. 12. limiting values 13. characteristics 13.1 operating condition range table 146. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit t amb ambient temperature ? 40 +150 ?c t stg storage temperature ? 40 +150 ?c v ddd digital supply voltage ? 0.5 +6 v v dda analog supply voltage ? 0.5 +6 v v dd(tvdd) tvdd supply voltage ? 0.5 +6 v ?v i ? input voltage (absolute value) on any digital pin to dvss ? 0.5 v ddd + 0.5 v on pin rx to avss ? 0.5 v dda + 0.5 v table 147. operating condition range symbol parameter conditions min typ max unit t amb ambient temperature - ? 25 +25 +85 ?c v ddd digital supply voltage dvss = avss = tvss = 0 v 4.5 5.0 5.5 v v dda analog supply voltage dvss = avss = tvss = 0 v 4.5 5.0 5.5 v v dd(tvdd) tvdd supply voltage dvss = avss = tvss = 0 v 3.0 5.0 5.5 v v esd electrostatic discharge voltage human body model (hbm); 1.5 k ? , 100 pf - - 1000 v machine model (mm); 0.75 ? h, 200 pf --100v
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 84 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 13.2 current consumption 13.3 pin characteristics 13.3.1 input pin characteristics pins d0 to d7, a0, and a1 have ttl input characteristics and behave as defined in table 149 . the digital input pins ncs, nwr, nrd, al e, a2, and mfin have schmitt trigger characteristics, and behave as defined in table 150 . table 148. current consumption symbol parameter conditions min typ max unit i ddd digital supply current idle command - 8 11 ma standby mode - 3 5 ma soft power-down mode - 800 1000 ? a hard power-down mode - 1 10 ? a i dda analog supply current idle command; receiver on - 25 40 ma idle command; receiver off - 12 15 ma standby mode - 10 13 ma soft power-down mode - 1 10 ? a hard power-down mode - 1 10 ? a i dd(tvdd) tvdd supply current continuous wave - - 150 ma pins tx1 and tx2 unconnected; tx1rfen and tx2rfen = logic 1 -5.57 ma pins tx1 and tx2 unconnected; tx1rfen and tx2rfen = logic 0 - 65 130 ? a table 149. standard input pin characteristics symbol parameter conditions min typ max unit i li input leakage current ? 1.0 - +1.0 ? a v th threshold voltage cmos: v ddd < 3.6 v 0.35v ddd - 0.65v ddd v ttl: 4.5 < v ddd 0.8 - 2.0 v table 150. schmitt trigger input pin characteristics symbol parameter conditions min typ max unit i li input leakage current ? 1.0 - +1.0 ? a v th threshold voltage positive-going threshold; ttl = 4.5 < v ddd 1.4 - 2.0 v cmos = v ddd < 3.6 v 0.65v ddd - 0.75v ddd v negative-going threshold; ttl = 4.5 < v ddd 0.8 - 1.3 v cmos = v ddd < 3.6 v 0.25v ddd -0.4v ddd v
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 85 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution pin rstpd has schmitt trigger cmos characteristics. in addition, it is internally filtered by a rc low-pass filter which causes a propagation delay on the reset signal. the analog input pin rx has the input capacitance and input voltage range shown in table 152 . 13.3.2 digital output pin characteristics pins d0 to d7, mfout and irq have cmos output characteri stics and behave as defined in ta b l e 1 5 3 . remark: pin irq can be configured as o pen collector which causes the v oh values to be no longer applicable. table 151. rstpd input pin characteristics symbol parameter conditions min typ max unit i li input leakage current ? 1.0 - +1.0 ? a v th threshold voltage positive-going threshold; cmos = v ddd < 3.6 v 0.65v ddd - 0.75v ddd v negative-going threshold; cmos = v ddd < 3.6 v 0.25v ddd -0.4v ddd v t pd propagation delay - - 20 ? s table 152. rx input capacitance and input voltage range symbol parameter conditions min typ max unit c i input capacitance - - 15 pf v i(dyn) dynamic input voltage v dda = 5 v; t amb = 25 ? c1.1-4.4v table 153. digital output pin characteristics symbol parameter conditions min typ max unit v oh high-level output voltage v ddd = 5 v; i oh = ? 1 ma 2.4 4.9 - v v ddd = 5 v; i oh = ? 10 ma 2.4 4.2 - v v ol low-level output voltage v ddd = 5 v; i ol = 1 ma - 25 400 mv v ddd = 5 v; i ol = 10 ma - 250 400 mv i o output current source or sink; v ddd =5v - - 10 ma
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 86 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 13.3.3 antenna driver output pin characteristics the source conductance of the antenna dr iver pins tx1 and tx2 for driving the high-level can be configured using the cwco nductance register?s gscfgcw[5:0] bits, while their source conductance for driving the low-level is constant. the antenna driver default configuration output characteristics are specified in table 154 . 13.4 ac electrical characteristics 13.4.1 separate read/write strobe bus timing table 154. antenna driver output pin characteristics symbol parameter conditions min typ max unit v oh high-level output voltage v dd(tvdd) = 5.0 v; i ol = 20 ma - 4.97 - v v dd(tvdd) = 5.0 v; i ol = 100 ma - 4.85 - v v ol low-level output voltage v dd(tvdd) = 5.0 v; i ol = 20 ma - 30 - mv v dd(tvdd) = 5.0 v; i ol = 100 ma - 150 - mv i o output current transmitter; continuous wave; peak-to-peak - - 200 ma table 155. timing specification for separate read/write strobe symbol parameter conditions min typ max unit t lhll ale high time 20 - - ns t avll address valid to ale low time 15 - - ns t llax address hold after ale low time 8--ns t llrwl ale low to read/write low time ale low to nrd or nwr low 15 - - ns t slrwl chip select low to read/write low time ncs low to nrd or nwr low 0--ns t rwhsh read/write high to chip select high time nrd or nwr high to ncs high 0--ns t rldv read low to data input valid time nrd low to data valid - - 65 ns t rhdz read high to data input high impedance time nrd high to data high-impedance - - 20 ns t wlqv write low to data output valid time nwr low to data valid - - 35 ns t whdx data output hold after write high time data hold time after nwr high 8--ns t rwlrwh read/write low time nrd or nwr 65 - - ns t avrwl address valid to read/write low time nrd or nwr low (set-up time) 30 - - ns t whax address hold after write high time nwr high (hold time) 8 - - ns t rwhrwl read/write high time 150 - - ns
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 87 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution remark: the signal ale is not relevant for separate address/data bus and the multiplexed addresses on the data bus do not care. the multiplexed address and data bus address lines (a0 to a2) must be connected as described in section 9.1.3 on page 8 . 13.4.2 common read/write strobe bus timing fig 19. separate read/write strobe timing diagram 001aaj638 t slrwl t rwhsh t rwhrwl t whdx t rhdz t wlqv t rldv t avrwl t whax t llax t avll t rwlrwh t llrwl t rwhrwl t lhll a0 to a2 a0 to a2 d0 to d7 d0 to d7 nwr nrd ncs ale a0 to a2 multiplexed address bus separated address bus table 156. common read/write st robe timing specification symbol parameter conditions min typ max unit t lhll ale high time 20 - - ns t avll address valid to ale low time 15 - - ns t llax address hold after ale low time 8 - - ns t lldsl ale low to data strobe low time nwr or nrd low 15 - - ns t sldsl chip select low to data strobe low time ncs low to nds low 0--ns t dshsh data strobe high to chip select high time 0--ns t dsldv data strobe low to data input valid time - - 65 ns t dshdz data strobe high to data input high impedance time - - 20 ns t dslqv data strobe low to data output valid time nds/ncs low - - 35 ns t dshqx data output hold after data strobe high time nds high (write cycle hold time) 8--ns t dshrwx rw hold after data strobe high time after nds high 8 - - ns t dsldsh data strobe low time nds/ncs 65 - - ns
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 88 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 13.4.3 epp bus timing t avdsl address valid to data strobe low time 30 - - ns t rhax address hold after read high time 8 - - ns t dshdsl data strobe high time period between write sequences 150 - - ns t wldsl write low to data strobe low time r/nw valid to nds low 8--ns fig 20. common read/write strobe timing diagram table 156. common read/write st robe timing specification ?continued symbol parameter conditions min typ max unit 001aaj639 t sldsl t dshsh t dshdsl t dshqx t dshdz t dsldv t dslqv t avdsl t rhax t llax t avll t dsldsh t lldsl t dshdsl t lhll t wldsl t dshrwx a0 to a2 a0 to a2 d0 to d7 d0 to d7 nrd r/nw ncs/nds ale a0 to a2 multiplexed address bus separated address bus table 157. common read/write stro be timing specification for epp symbol parameter conditions min typ max unit t aslash address strobe low time nastrb 20 - - ns t avash address valid to address strobe high time multiplexed address bus set-up time 15 - - ns t ashav address valid after address strobe high time multiplexed address bus hold time 8- - ns t sldsl chip select low to data strobe low time ncs low to ndstrb low 0- - ns t dshsh data strobe high to chip select high time ndstrb high to ncs high 0- - ns t dsldv data strobe low to data input valid time read cycle - - 65 ns
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 89 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution remark: figure 21 does not distinguish between the address write cycle and a data write cycle. the timings for the address write and data write cycle are different. in epp mode, the address lines (a0 to a2) must be connected as described in section 9.1.3 on page 8 . t dshdz data strobe high to data input high impedance time read cycle - - 20 ns t dslqv data strobe low to data output valid time ndstrb low - - 35 ns t dshqx data output hold after data strobe high time ncs high 8 - - ns t dshwx write hold after data strobe high time nwrite 8 - - ns t dsldsh data strobe low time ndstrb 65 - - ns t wldsl write low to data strobe low time nwrite valid to ndstrb low 8- - ns t dsl-waith data strobe low to wait high time ndstrb low to nwrite high - - 75 ns t dsh-waitl data strobe high to wait low time ndstrb high to nwrite low - - 75 ns fig 21. timing diagram for common read/write strobe; epp table 157. common read/write stro be timing specification for epp ?continued symbol parameter conditions min typ max unit 001aaj640 nwait t dsl-waith t dsldv t dslqv t wldsl t sldsl t dshsh t dsldsh d0 to d7 a0 to a7 t dshqx t dshdz t dsh-waitl t dshwx d0 to d7 ndstrb nastrb nwrite ncs
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 90 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 13.4.4 clock frequency the clock input is pin oscin. the clock applied to the mfrc500 acts as a time constant for the synchronous system?s encoder and decoder. the stab ility of the clock frequency is an important factor for ensuring proper performance. to obtain highes t performance, clock jitter must be as small as possible. this is best achieved usi ng the internal oscillator buffer and the recommended circuitry; see section 9.8 on page 26 . 14. eeprom characteristics the eeprom size is 32 ? 16 ? 8 = 4096 bit. table 158. clock frequency symbol parameter conditions min typ max unit f clk clock frequency checked by the clock filter -13.56-mhz ? clk clock duty cycle 40 50 60 % t jit jitter time of clock edges - - 10 ps table 159. eeprom characteristics symbol parameter conditions min typ max unit n endu(w_er) write or erase endurance er ase/write cycles 100.000 - - hz t ret retention time t amb ? 55 ?c 10 - - year t er erase time - - 2.9 ms t a(w) write access time - - 2.9 ms
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 91 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 15. application information 15.1 typical application 15.1.1 circuit diagram figure 22 shows a typical application where the antenna is directly matched to the mfrc500: 15.1.2 circuit description the matching circuit consists of an emc low- pass filter (l0 and c0), matching circuitry (c1 and c2), a receiver circuit (r1, r2, c3 and c4) and the antenna itself. refer to the following application notes for mo re detailed information about designing and tuning an antenna. ? micore reader ic family; directly matched antenna design ref. 1 ? mifare (14443 a) 13.56 mhz rfid proximity antennas ref. 2 . 15.1.2.1 emc low-pass filter the mifare system operates at a frequency of 13.56 mhz. this frequency is generated by a quartz oscillator to clock the mfrc500. it is also th e basis for driv ing the antenna using the 13.56 mhz energy carrier. this not only causes power emissions at 13.56 mhz, it also emits power at higher harmonics. international emc regulations define the amplitude of the emitted power over a broad frequency range. to meet these regulations, appropriate filtering of the output signal is required. fig 22. application example circuit diagram: directly matched antenna 001aak625 dvdd rstpd avdd tvdd dvdd reset avdd tvdd dvss control lines data bus irq oscin oscout 13.56 mhz avss vmid rx tx2 tvss tx1 irq 15 pf 15 pf c0 c0 c2a c2b c3 r2 r1 l0 l0 c1 c1 c4 100 nf microprocessor bus microprocessor device
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 92 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution a multilayer board is recommended to im plement a low-pass f ilter as shown in figure 22 . the low-pass filter consists of the components l0 and c0. the recommended values are given in application notes micore reader ic family; directly matched antenna design ref. 1 and mifare (14443 a) 13.56 mhz rfid proximity antennas ref. 2 . remark: to achieve best performance, all components must be at least equal in quality to those recommended. remark: the layout has a major influence on the overall performance of the filter. 15.1.2.2 antenna matching due to the impedance transformation of the low-pass filter, the antenna coil has to be matched to a given impedance. the matching elements c1 and c2 can be estimated and have to be fine tuned depending on the design of the antenna coil. the correct impedance matching is important to ensure optimum performance. the overall quality factor has to be considered to guarantee a proper iso/iec 14443 a communication scheme. environmental influences have to considered and common emc design rules. refer to application notes micore reader ic family; directly matched antenna design ref. 1 and mifare (14443 a) 13.56 mhz rfid proximity antennas ref. 2 for details. remark: do not exceed the current limits (i dd(tvdd) ), otherwise the chip might be destroyed. remark: the overall 13.56 mhz rfid proximity antenna design in combination with the mfrc500 ic does not require any specialist rf knowledge. however, all relevant parameters have to be considered to guarantee optimum performance and international emc compliance. 15.1.2.3 receiver circuit the internal receiver of the mfrc500 makes use of both subcarrier load modulation side-bands. no external filtering is required. it is recommended to use the internally generated vmid potential as the input potential for pin rx. this vmid dc voltage level has to be coupled to pin rx using resistor (r2). to provide a stable dc reference voltage, a capacitor (c4) must be connected between vmid and ground. the ac voltage divider of r1 + c3 and r2 has to be designed taking in to account the ac voltage limits on pin rx. depending on the antenna coil design and the impedance, matching the voltage at the antenna coil will differ. ther efore the reco mmended way to design the receiver circuit is to use the given values for r1, r2, and c3; refer to application note; mifare (14443 a) 13.56 mhz rfid proximity antennas ref. 2 . the voltage on pin rx can be altered by varying r1 within the given limits. remark: r2 is ac connected to ground using c4.
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 93 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 15.1.2.4 antenna coil the precise calculation of the antenna coil? s inductance is not practicable but the inductance can be estimated using equation 10 . we recommend designing an antenna that is either circular or rectangular. (10) ? l 1 = length of one turn of the conductor loop ? d 1 = diameter of the wire or width of the pcb conductor, respectively ? k = antenna shape factor (k = 1.07 for circular antennas and k = 1.47 for square antennas) ? n 1 = number of turns ? ln = natural logarithm function the values of the antenna in ductance, resistance, and capa citance at 13.56 mhz depend on various parame ters such as: ? antenna construction (type of pcb) ? thickness of conductor ? distance between the windings ? shielding layer ? metal or ferrite in the near environment therefore a measurement of these parameters under real life conditions or at least a rough measurement and a tuning procedure is highly recommended to guarantee adequate performance. refe r to application notes micore reader ic family; directly matched antenna design ref. 1 and mifare (14443 a) 13.56 mhz rfid proximity antennas ref. 2 for details. 15.2 test signals the mfrc500 allows different kinds of signal measurements. these measurements can be used to check the internally generated an d received signals using the serial signal switch as described in section 9.11 on page 32 . in addition, the mfrc500 enables users to select between: ? internal analog signals for measurement on pin aux ? internal digital signals for observation on pin mfout (based on register selections) these measurements can be helpful during the design-in phase to optimize the receiver?s behavior, or for test purposes. l 1 nh ?? 2 = i 1 cm ?? i 1 d 1 ------ ?? ln k ? ?? ?? n 1 1.8 ??
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 94 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 15.2.1 measurements using the serial signal switch using the serial signal switch on pin mfout, data is observed that is sent to the card or received from the card. table 160 gives an overview of the different signals available. 15.2.1.1 tx control figure 23 shows as an example of an iso/iec 14443 a communication. the signal is measured on pin mfout using the serial signal switch to control the data sent to the card. sett ing the flag mfoutselect[2:0] = 3 sends the data to the card coded as nrz. setting mfoutselect[2:0] = 2 show s the data as a miller coded signal. the rfout signal is measured directly on the antenna and gives the rf signal pulse shape. refer to application note directly matched antenna - excel calculation ( ref. 3 ) for detail information on the rf signal pulse. table 160. signal routed to pin mfout signaltomfout mfoutselect signal routed to pin mfout 00low 01high 02envelope 0 3 transmit nrz 0 4 manchester with subcarrier 0 5 manchester 0 6 reserved 0 7 reserved 1 x digital test signal
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 95 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 15.2.1.2 rx control figure 24 shows an example of iso/iec 14443 a communication which represents the beginning of a card?s answer to a request signal. the rf signal shows the rf voltage measured directly on the antenna so that the card?s load modulation is visible. setting mfouts elect[2:0] = 4 shows the manchester decoded signal with subcarrier. setting mfoutsel ect[2:0] = 5 shows the manchester decoded signal. (1) mfoutselect[2:0] = 3; serial data stream; 2 v per division. (2) mfoutselect[2:0] = 2; serial data stream; 2 v per division. (3) rfout; 1 v per division. fig 23. tx control signals 001aak626 (1) (2) (3) 10 s per division
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 96 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 15.2.2 analog test signals the analog test signals can be routed to pin aux by selecting them using the testanaselect register te stanaoutsel[4:0] bits. (1) rfout; 1 v per division. (2) mfoutselect[2:0] = 4; manchester with subcarrier; 2 v per division. (3) mfoutselect[2:0] = 5; manchester; 2 v per division. fig 24. rx control signals 001aak627 10 s per division (1) (2) (3) table 161. analog test signal selection value signal name description 0 vmid voltage at internal node vmid 1 vbandgap internal reference voltage generated by the bandgap 2 vrxfolli output signal from the demodulator using the i-clock 3 vrxfollq output signal from the demodulator using the q-clock 4 vrxampi i-channel subcarrier signal amplified and filtered 5 vrxampq q-channel subcarrier signal amplified and filtered 6 vcorrni output signal of n-channel correlator fed by the i-channel subcarrier signal 7 vcorrnq output signal of n-channel correlator fed by the q-channel subcarrier signal 8 vcorrdi output signal of d-channel correlator fed by the i-channel subcarrier signal 9 vcorrdq output signal of d-channel correlator fed by the q-channel subcarrier signal a vevall evaluation signal from the left half-bit
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 97 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 15.2.3 digital test signals digital test signals can be routed to pin mfout by setting bit signaltomfout = logic 1. a digital test signal is selected using the test digiselect register test digisignalsel[6:0] bits. the signals selected by the testdigisignalsel[6:0] bits are shown in table 162 . if test signals are not used, the testdigise lect register address value must be 00h. remark: all other values for testdigisignalsel[6:0] are for production test purposes only. 15.2.4 analog and digital test signal examples figure 25 shows a mifare card?s answer to a request command using the q-clock receiving path. rx reference is given to show the manchester modulated signal on pin rx. the signal is demodulated and amplified in th e receiver circuitry. signal vrxampq is the amplified side-band signal using the q-clock for demodulation. the signals vcorrdq and vcorrnq were generated in the correlation ci rcuitry. they are processed further in the evaluation and digitizer circuitry. signals vevalr and vevall show the evaluation of the signal?s right and left half-bit. finally, the digital test signal s_data shows t he received data. this is then sent to the internal digital circuit and s_valid which indicates the received data stream is valid. b vevalr evaluation signal from the right half-bit c vtemp temperature voltage derived from band gap d reserved reserved for future use e reserved reserved for future use f reserved reserved for future use table 161. analog test signal selection ?continued value signal name description table 162. digital test signal selection testdigisignalsel [6:0] signal name description f4h s_data data received from the card e4h s_valid when logic 1 is returned the s_data and s_coll signals are valid d4h s_coll when logic 1 is returned a collision has been detected in the current bit c4h s_clock internal serial clock: during transmission, this is the encoder clock during reception this is the receiver clock b5h rd_sync internal synchronized read signal which is derived from the parallel microprocessor interface a5h wr_sync internal synchronized write signal which is derived from the parallel microprocessor interface 96h int_clock internal 13.56 mhz clock 00h no test signal output as defi ned by the mfoutselect register mfoutselect[2:0] bits routed to pin mfout
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 98 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution fig 25. iso/iec 14443 a receiving path q-clock 001aak628 rx reference vrxampq vcorrdq vcorrnq vevalr vevall s_data s_valid 50 s per division
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 99 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 16. package outline fig 26. package outline sot287-1 unit a max. a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 2.65 0.1 0.25 0.01 1.4 0.055 0.3 0.1 2.45 2.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.2 1.0 0.95 0.55 8 0 o o 0.25 0.1 0.004 0.25 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot287-1 mo-119 (1) 0.012 0.004 0.096 0.089 0.02 0.01 0.05 0.047 0.039 0.419 0.394 0.30 0.29 0.81 0.80 0.011 0.007 0.037 0.022 0.01 0.01 0.043 0.016 w m b p d h e z e c v m a x a y 32 17 16 1 a a 1 a 2 l p q detail x l (a ) 3 e pin 1 index 0 5 10 mm scale so32: plastic small outline package; 32 leads; body width 7.5 mm sot287-1 00-08-17 03-02-19
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 100 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 17. abbreviations 18. references [1] application note ? micore reader ic family; directly matched antenna design. [2] application note ? mifare (14443 a) 13.56 mhz rfid proximity antennas. [3] application note ? directly matched antenn a - excel calculation. [4] iso standard ? iso/iec 14443 identification cards - contactless integrated circuit(s) cards - prox imity cards, part 1-4. [5] application note ? mifare implementation of higher baud rates. table 163. abbreviations and acronyms acronym description ask amplitude-shift keying cmos complementary metal-oxide semiconductor crc cyclic redundancy check eof end of frame epp enhanced parallel port etu elementary time unit fifo first in, first out hbm human body model lsb least significant bit mm machine model msb most significant bit nrz none return to zero por power-on reset pcd proximity coupling device picc proximity integrated circuit card sof start of frame spi serial peripheral interface
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 101 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 19. revision history table 164. revision history document id release date data sheet status change notice supersedes mfrc500 v. 3.4 20140211 product data sheet - mfrc500_33 modifications: ? descriptive title changed ? section 2 ? general description ? : updated mfrc500_33 20100315 product data sheet - 048032 modifications: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors ? legal texts have been adapted to the new company name where appropriate ? this version supersedes all previous revisions. ? the symbols for electrical characteristics and their parameters have been updated to meet the nxp semiconductors? guidelines ? a number of inconsistencies in pin, register and bit names have been eliminated from the data sheet ? all drawings have been updated ? section 5 ? quick reference data ? on page 3 : section added ? section 15.1.2.4 ? antenna coil ? on page 93 : added missing formula and updated the last clause ? section 16 ? package outline ? on page 99 : updated ? section 18 ? references ? on page 100 : added section and updated the references in the document 048032 20051201 product data sheet - 048031 048031 20040501 product data sheet - 048030 048030 20030301 preliminary data sheet - 048020 048020 20010131 objective data sheet - 048010 048010 20040430 objective data sheet - -
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 102 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 20.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 20.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 103 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 20.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. mifare ? is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 104 of 110 continued >> nxp semiconductors mfrc500 the "original" mifare reader solution 22. tables table 1. quick reference data . . . . . . . . . . . . . . . . . . . . .3 table 2. ordering information . . . . . . . . . . . . . . . . . . . . .3 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 4. supported micropr ocessor and epp interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 5. connection scheme for detecting the parallel interface type . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 6. eeprom memory organization diagram . . . . .10 table 7. product information field byte allocation . . . . . 11 table 8. product information field byte description . . . . 11 table 9. product type identification definition . . . . . . . . 11 table 10. byte assignment for register initialization at start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 11. shipment content of startup configuration file .12 table 12. byte assignment for register initialization at startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 13. fifo buffer access . . . . . . . . . . . . . . . . . . . . .15 table 14. associated fifo buffer registers and flags . . .16 table 15. interrupt sources . . . . . . . . . . . . . . . . . . . . . . .17 table 16. interrupt control registers . . . . . . . . . . . . . . . .17 table 17. associated interrupt request system registers and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 18. associated timer unit registers and flags . . . . .23 table 19. signal on pins during hard power-down . . . . .23 table 20. pin tx1 configurations . . . . . . . . . . . . . . . . . .27 table 21. pin tx2 configurations . . . . . . . . . . . . . . . . . .27 table 22. tx1 and tx2 source resistance of n-channel driver transistor against gscfgcw or gscfgmod . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 23. gain factors for the inte rnal amplifier . . . . . . . .32 table 24. decodersource[1:0] values . . . . . . . . . . . . . . .34 table 25. modulatorsource[1:0] va lues . . . . . . . . . . . . . .34 table 26. mfoutselect[2:0] values . . . . . . . . . . . . . . . .34 table 27. register settings to enable use of the analog circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 28. dedicated address bus: assembling the register address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 29. multiplexed address bus: assembling the register address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 30. behavior and designation of register bits . . . . .38 table 31. mfrc500 register overview . . . . . . . . . . . . . .39 table 32. mfrc500 register flags overview . . . . . . . . . .41 table 33. page register (addres s: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h) reset value: 1000 0000b, 80h bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 34. page register bit descrip tions . . . . . . . . . . . . .43 table 35. command register (address: 01h) reset value: x000 0000b, x0h bit allocation . . . . . . . . . . . . .44 table 36. command register bit descriptions . . . . . . . . . 44 table 37. fifodata register (address: 02h) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 44 table 38. fifodata register bit descriptions . . . . . . . . . 44 table 39. primarystatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation . . . . . . . . . . . . 45 table 40. primarystatus register bit descriptions . . . . . . 45 table 41. fifolength register (address: 04h) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . 46 table 42. fifolength bit descriptions . . . . . . . . . . . . . . 46 table 43. secondarystatus regi ster (address: 05h) reset value: 01100 000b, 60h bit allocation . . . . . . . 46 table 44. secondarystatus register bit descriptions . . . . 46 table 45. interrupten register (address: 06h) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . 47 table 46. interrupten register bit descriptions . . . . . . . . 47 table 47. interruptrq register (address: 07h) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . 47 table 48. interruptrq register bi t descriptions . . . . . . . . 47 table 49. control register (address: 09h) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . . . . . . 48 table 50. control register bit de scriptions . . . . . . . . . . . 48 table 51. errorflag register (address: 0ah) reset value: 0100 0000b, 40h bit allocation . . . . . . . . . . . . 49 table 52. errorflag register bit descriptions . . . . . . . . . . 49 table 53. collpos register (address: 0bh) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . . . . . . 50 table 54. collpos register bit descriptions . . . . . . . . . . . 50 table 55. timervalue register (address: 0ch) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 50 table 56. timervalue register bit descriptions . . . . . . . . 50 table 57. crcresultlsb register (address: 0dh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 50 table 58. crcresultlsb register bit descriptions . . . . . 50 table 59. crcresultmsb register (address: 0eh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 51 table 60. crcresultmsb register bit descriptions . . . . 51 table 61. bitframing register (address: 0fh) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . 51 table 62. bitframing register bit descriptions . . . . . . . . . 51 table 63. txcontrol register (address: 11h) reset value: 0101 1000b, 58h bit allocation . . . . . . . . . . . . 52 table 64. txcontrol register bit descriptions . . . . . . . . . 52 table 65. cwconductance register (address: 12h) reset value: 0011 1111b, 3fh bit allocation . . . . . . . 53 table 66. cwconductance register bit descriptions . . . . 53 table 67. preset13 register (address: 13h) reset value: 0011 1111b, 3fh bit allocation . . . . . . . . . . . . . 53
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 105 of 110 continued >> nxp semiconductors mfrc500 the "original" mifare reader solution table 68. preset13 register bit descriptions . . . . . . . . . .53 table 69. preset14 register (address: 14h) reset value: 0001 1001b, 19h bit allocation . . . . . . . . . . . . .53 table 70. preset14 register bit descriptions . . . . . . . . . .53 table 71. modwidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation . . . . . . . . . . . . .54 table 72. modwidth register bit descriptions . . . . . . . . . .54 table 73. preset16 register (address: 16h) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . .54 table 74. preset16 register bit descriptions . . . . . . . . . .54 table 75. preset17 register (address: 17h) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . .54 table 76. preset17 register bit descriptions . . . . . . . . . .54 table 77. rxcontrol1 register (address: 19h) reset value: 0111 0011b, 73h bit allocation . . . . . . . . . . . . .55 table 78. rxcontrol1 register bit descriptions . . . . . . . . .55 table 79. decodercontrol regi ster (address: 1ah) reset value: 0000 1000b, 08h bit allocation . . . . . . .55 table 80. decodercontrol register bit descriptions . . . . .55 table 81. bitphase register (a ddress: 1bh) reset value: 1010 1101b, adh bit allocation . . . . . . . . . . . .56 table 82. bitphase register bit de scriptions . . . . . . . . . .56 table 83. rxthreshold register (address: 1ch) reset value: 1111 1111b, ffh bit allocation . . . . . . . . . . . . . 56 table 84. rxthreshold register bit descriptions . . . . . . .56 table 85. preset1d register (address: 1dh) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . .56 table 86. preset1d register bit descriptions . . . . . . . . . .56 table 87. rxcontrol2 register (address: 1eh) reset value: 0100 0001b, 41h bit allocation . . . . . . . . . . . . .57 table 88. rxcontrol2 register bit descriptions . . . . . . . . .57 table 89. clockqcontrol regi ster (address: 1fh) reset value: 000x xxxxb, xxh bit allocation . . . . . . . .57 table 90. clockqcontrol register bit descriptions . . . . . .57 table 91. rxwait register (address: 21h) reset value: 0000 0101b, 06h bit allocation . . . . . . . . . . . . . . . . .58 table 92. rxwait register bit descriptions . . . . . . . . . . . .58 table 93. channelredundancy register (address: 22h) reset value: 0000 0011b, 03h bit allocation . . .58 table 94. channelredundancy bit descriptions . . . . . . .58 table 95. crcpresetlsb register (address: 23h) reset value: 0101 0011b, 63h bit allocation . . . . . . .59 table 96. crcpresetlsb register bit descriptions . . . . .59 table 97. crcpresetmsb register (address: 24h) reset value: 0101 0011b, 63h bit allocation . . . . . . .59 table 98. crcpresetmsb bit descriptions . . . . . . . . . . .59 table 99. preset25 register (address: 25h) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . .59 table 100. preset25 register bit descriptions . . . . . . . . . .60 table 101. mfoutselect register (address: 26h) reset value: 0000 0000b, 00h bit allocation . . . . . . .60 table 102. mfoutselect register bit descriptions . . . . . 60 table 103. preset27 (address: 27h) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 60 table 104. preset27 register bit descriptions . . . . . . . . . 60 table 105. fifolevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation . . . . . . . . . . . . 61 table 106. fifolevel register bit descriptions . . . . . . . . 61 table 107. timerclock register (address: 2ah) reset value: 0000 0111b, 07h bit allocation . . . . . . . . . . . . . 61 table 108. timerclock register bit descriptions . . . . . . . . 61 table 109. timercontrol register (address: 2bh) reset value: 0000 0110b, 06h bit allocation . . . . . . . . . . . . 62 table 110. timercontrol register bit descriptions . . . . . . . 62 table 111. timerreload register (address: 2ch) reset value: 0000 1010b, 0ah bit allocation . . . . . . . . . . . . 62 table 112. timerreload register bit descriptions . . . . . . . 62 table 113. irqpinconfig register (address: 2dh) reset value: 0000 0010b, 02h bit allocation . . . . . . . . . . . . 63 table 114. irqpinconfig register bit descriptions . . . . . . 63 table 115. preset2e register (address: 2eh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 63 table 116. preset2f register (address: 2fh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 63 table 117. reserved registers (address: 31h, 32h, 33h, 34h, 35h, 36h, 37h) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 118. reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 64 table 119. testanaselect register (address: 3ah) reset value: 0000 0000b, 00h bit allocation . . . . . . . 64 table 120. testanaselect bit descriptions . . . . . . . . . . . . 64 table 121. reserved register (address: 3bh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 65 table 122. reserved register (address: 3ch) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 65 table 123. testdigiselect register (address: 3dh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 65 table 124. testdigiselect register bit descriptions . . . . . 65 t a ble 125. reserved register (address: 3eh, 3fh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 66 table 126. mfrc500 commands overview . . . . . . . . . . . 66 table 127. startup command 3fh . . . . . . . . . . . . . . . . . . 68 table 128. idle command 00h . . . . . . . . . . . . . . . . . . . . . 68 table 129. transmit command 1ah . . . . . . . . . . . . . . . . . 69 table 130. transmission of frames of more than 64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 131. receive command 16h . . . . . . . . . . . . . . . . . 72 table 132. return values for bit-collision positions . . . . . 74 table 133. communication error table . . . . . . . . . . . . . . . 75 table 134. transceive command 1eh . . . . . . . . . . . . . . . 75 table 135. meaning of modemstate . . . . . . . . . . . . . . . . 75
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 106 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution table 136. writee2 command 01h . . . . . . . . . . . . . . . . . .77 table 137. reade2 command 03h . . . . . . . . . . . . . . . . . .79 table 138. loadconfig command 07h . . . . . . . . . . . . . . .79 table 139. calccrc command 12h . . . . . . . . . . . . . . . . .80 table 140. crc coprocessor parameters . . . . . . . . . . . .80 table 141. errorflag register error flags overview . . . . . .81 table 142. loadkeye2 command 0bh . . . . . . . . . . . . . . .81 table 143. loadkey command 19h . . . . . . . . . . . . . . . . .81 table 144. authent1 command 0ch . . . . . . . . . . . . . . . . .82 table 145. authent2 command 14h . . . . . . . . . . . . . . . . .82 table 146. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .83 table 147. operating condition range . . . . . . . . . . . . . . . .83 table 148. current consumption . . . . . . . . . . . . . . . . . . . .84 table 149. standard input pin characteristics . . . . . . . . . .84 table 150. schmitt trigger input pin characteristics . . . . .84 table 151. rstpd input pin characteristics . . . . . . . . . . .85 table 152. rx input capacitance and input voltage range 85 table 153. digital output pin characteristics . . . . . . . . . . .85 table 154. antenna driver output pin characteristics . . . .86 table 155. timing specificatio n for separate read/write strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 table 156. common read/write strobe timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . .87 table 157. common read/write strobe timing specification for epp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 table 158. clock frequency . . . . . . . . . . . . . . . . . . . . . . .90 table 159. eeprom characteristics . . . . . . . . . . . . . . . .90 table 160. signal routed to pin mfout . . . . . . . . . . . . . .94 table 161. analog test signal selection . . . . . . . . . . . . . .96 table 162. digital test signal selection . . . . . . . . . . . . . . .97 table 163. abbreviations and acronyms . . . . . . . . . . . . .100 table 164. revision history . . . . . . . . . . . . . . . . . . . . . . .101
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 107 of 110 nxp semiconductors mfrc500 the "original" mifare reader solution 23. figures fig 1. mfrc500 block diagram . . . . . . . . . . . . . . . . . . . .4 fig 2. mfrc500 pin configuration . . . . . . . . . . . . . . . . . .5 fig 3. connection to microprocessor: separate read and write strobes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 fig 4. connection to microprocessor: common read and write strobes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 fig 5. connection to microprocessor: epp common read/write strobes and handshake. . . . . . . . . . . . .9 fig 6. key storage format . . . . . . . . . . . . . . . . . . . . . . .14 fig 7. timer module block diagram . . . . . . . . . . . . . . . .20 fig 8. the startup procedure. . . . . . . . . . . . . . . . . . . . .25 fig 9. quartz clock connection . . . . . . . . . . . . . . . . . . .26 fig 10. receiver circuit block diag ram . . . . . . . . . . . . . . .30 fig 11. automatic q-clock calibration . . . . . . . . . . . . . . .31 fig 12. serial signal switch block diagram . . . . . . . . . . . .33 fig 13. crypto1 key handling block diagram . . . . . . . . . .36 fig 14. transmitting bit oriented frames . . . . . . . . . . . . .70 fig 15. timing for transmitting byte oriented frames . . . .71 fig 16. timing for transmitting bit oriented frames. . . . . .71 fig 17. card communication state diagram . . . . . . . . . . .76 fig 18. eeprom programming timing diagram. . . . . . . .78 fig 19. separate read/write stro be timing diagram . . . . .87 fig 20. common read/write strobe timing diagram . . . . .88 fig 21. timing diagram for common read/write strobe; epp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 fig 22. application example circuit diagram: directly matched antenna . . . . . . . . . . . . . . . . . . . . . . . . .91 fig 23. tx control signals . . . . . . . . . . . . . . . . . . . . . . . .95 fig 24. rx control signals . . . . . . . . . . . . . . . . . . . . . . . .96 fig 25. iso/iec 14443 a receiving path q-clock. . . . . . .98 fig 26. package outline sot287-1 . . . . . . . . . . . . . . . . .99
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 108 of 110 continued >> nxp semiconductors mfrc500 the "original" mifare reader solution 24. contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 general description . . . . . . . . . . . . . . . . . . . . . . 1 3 features and benefits . . . . . . . . . . . . . . . . . . . . 2 3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 quick reference data . . . . . . . . . . . . . . . . . . . . . 3 6 ordering information . . . . . . . . . . . . . . . . . . . . . 3 7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 8.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 functional description . . . . . . . . . . . . . . . . . . . 7 9.1 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.1 overview of supported microprocessor interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.2 automatic microprocessor interface detection . 7 9.1.3 connection to different microprocessor types . 8 9.1.3.1 separate read and write strobe . . . . . . . . . . . . 8 9.1.3.2 common read and write strobe . . . . . . . . . . . . 9 9.1.3.3 common read and write strobe: epp with handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9.2 memory organization of the eeprom . . . . . . 10 9.2.1 product information field (read only). . . . . . . . 11 9.2.2 register initialization f iles (read/write) . . . . . . 11 9.2.2.1 startup register initiali zation file (read/write) . 11 9.2.2.2 factory default star tup register initialization file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9.2.2.3 register initialization f ile (read/write) . . . . . . . 13 9.2.3 crypto1 keys (write only) . . . . . . . . . . . . . . . . 13 9.2.3.1 key format . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9.2.3.2 storage of keys in the eeprom . . . . . . . . . . 14 9.3 fifo buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9.3.1 accessing the fifo buffer . . . . . . . . . . . . . . . 14 9.3.1.1 access rules . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9.3.2 controlling the fifo buffer . . . . . . . . . . . . . . . 15 9.3.3 fifo buffer status information . . . . . . . . . . . . 15 9.3.4 fifo buffer registers and flags . . . . . . . . . . . . 16 9.4 interrupt request system . . . . . . . . . . . . . . . . . 16 9.4.1 interrupt sources overview . . . . . . . . . . . . . . . 16 9.4.2 interrupt request handling. . . . . . . . . . . . . . . . 17 9.4.2.1 controlling interrupts and getting their status . 17 9.4.2.2 accessing the interrupt registers . . . . . . . . . . 17 9.4.3 configuration of pin irq . . . . . . . . . . . . . . . . . 18 9.4.4 register over view interrupt request system . . 18 9.5 timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.5.1 timer unit implementation . . . . . . . . . . . . . . . 19 9.5.1.1 timer unit block diagram . . . . . . . . . . . . . . . . 19 9.5.1.2 controlling the timer unit . . . . . . . . . . . . . . . . 20 9.5.1.3 timer unit clock and period . . . . . . . . . . . . . . 21 9.5.1.4 timer unit status. . . . . . . . . . . . . . . . . . . . . . . 21 9.5.2 using the timer unit functions. . . . . . . . . . . . . 22 9.5.2.1 time-out and watchdog counters . . . . . . . . . 22 9.5.2.2 stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.5.2.3 programmable one shot timer and periodic trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.5.3 timer unit registers . . . . . . . . . . . . . . . . . . . . 23 9.6 power reduction modes . . . . . . . . . . . . . . . . . 23 9.6.1 hard power-down. . . . . . . . . . . . . . . . . . . . . . 23 9.6.2 soft power-down mode . . . . . . . . . . . . . . . . . 24 9.6.3 standby mode . . . . . . . . . . . . . . . . . . . . . . . . 24 9.6.4 automatic receiver power-d own. . . . . . . . . . . 24 9.7 startup phase . . . . . . . . . . . . . . . . . . . . . . . . 25 9.7.1 hard power-down phase . . . . . . . . . . . . . . . . 25 9.7.2 reset phase. . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.7.3 initialization phase . . . . . . . . . . . . . . . . . . . . . 25 9.7.4 initializing the parallel interface type . . . . . . . 25 9.8 oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . 26 9.9 transmitter pins tx1 and tx2 . . . . . . . . . . . . 27 9.9.1 configuring pins tx1 and tx2. . . . . . . . . . . . 27 9.9.2 antenna operating distance versus power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.9.3 antenna driver output source resistance . . . . 28 9.9.3.1 source resistance table . . . . . . . . . . . . . . . . . 28 9.9.3.2 calculating the relative source resistance . . . 29 9.9.3.3 calculating the effective source resistance . . 29 9.9.4 pulse width. . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.10 receiver circuit . . . . . . . . . . . . . . . . . . . . . . . 30 9.10.1 receiver circuit block di agram . . . . . . . . . . . . 30 9.10.2 receiver operation. . . . . . . . . . . . . . . . . . . . . 31 9.10.2.1 automatic q-clock calibration . . . . . . . . . . . . 31 9.10.2.2 amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.10.2.3 correlation circuitry . . . . . . . . . . . . . . . . . . . . 32 9.10.2.4 evaluation and digitizer circuitry . . . . . . . . . . 32 9.11 serial signal switch . . . . . . . . . . . . . . . . . . . . 33 9.11.1 serial signal switch bl ock diagram . . . . . . . . . 33 9.11.2 serial signal switch registers . . . . . . . . . . . . . 34 9.11.2.1 active antenna concept . . . . . . . . . . . . . . . . . 35 9.11.2.2 driving both rf parts . . . . . . . . . . . . . . . . . . . 35 9.12 mifare authentication and crypto1 . . . . . . . 35 9.12.1 crypto1 key handling . . . . . . . . . . . . . . . . . . . 36 9.12.2 authentication procedure . . . . . . . . . . . . . . . . 36 10 mfrc500 registers . . . . . . . . . . . . . . . . . . . . . 37 10.1 register addressing modes . . . . . . . . . . . . . . 37 10.1.1 page registers . . . . . . . . . . . . . . . . . . . . . . . . 37 10.1.2 dedicated address bus . . . . . . . . . . . . . . . . . 37
mfrc500 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 11 february 2014 048034 109 of 110 continued >> nxp semiconductors mfrc500 the "original" mifare reader solution 10.1.3 multiplexed address bus . . . . . . . . . . . . . . . . . 37 10.2 register bit behavior. . . . . . . . . . . . . . . . . . . . 38 10.3 register overview . . . . . . . . . . . . . . . . . . . . . . 39 10.4 mfrc500 register flags ov erview. . . . . . . . . . 41 10.5 register descriptions . . . . . . . . . . . . . . . . . . . 43 10.5.1 page 0: command and status . . . . . . . . . . . . 43 10.5.1.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.5.1.2 command register . . . . . . . . . . . . . . . . . . . . . 44 10.5.1.3 fifodata register . . . . . . . . . . . . . . . . . . . . . . 44 10.5.1.4 primarystatus register . . . . . . . . . . . . . . . . . . 45 10.5.1.5 fifolength register . . . . . . . . . . . . . . . . . . . . 46 10.5.1.6 secondarystatus register . . . . . . . . . . . . . . . . 46 10.5.1.7 interrupten register . . . . . . . . . . . . . . . . . . . . . 47 10.5.1.8 interruptrq register. . . . . . . . . . . . . . . . . . . . . 47 10.5.2 page 1: control and status . . . . . . . . . . . . . . . 48 10.5.2.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.5.2.2 control register . . . . . . . . . . . . . . . . . . . . . . . . 48 10.5.2.3 errorflag register . . . . . . . . . . . . . . . . . . . . . . 49 10.5.2.4 collpos register . . . . . . . . . . . . . . . . . . . . . . . 50 10.5.2.5 timervalue register. . . . . . . . . . . . . . . . . . . . . 50 10.5.2.6 crcresultlsb register . . . . . . . . . . . . . . . . . 50 10.5.2.7 crcresultmsb register . . . . . . . . . . . . . . . . . 51 10.5.2.8 bitframing register . . . . . . . . . . . . . . . . . . . . . 51 10.5.3 page 2: transmitter and control . . . . . . . . . . . 52 10.5.3.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.5.3.2 txcontrol register . . . . . . . . . . . . . . . . . . . . . . 52 10.5.3.3 cwconductance register . . . . . . . . . . . . . . . . 53 10.5.3.4 preset13 register . . . . . . . . . . . . . . . . . . . . . . 53 10.5.3.5 preset14 register . . . . . . . . . . . . . . . . . . . . . . 53 10.5.3.6 modwidth register. . . . . . . . . . . . . . . . . . . . . . 54 10.5.3.7 preset16 register . . . . . . . . . . . . . . . . . . . . . . 54 10.5.3.8 preset17 register . . . . . . . . . . . . . . . . . . . . . . 54 10.5.4 page 3: receiver and decoder control . . . . . . 55 10.5.4.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.5.4.2 rxcontrol1 register. . . . . . . . . . . . . . . . . . . . . 55 10.5.4.3 decodercontrol register . . . . . . . . . . . . . . . . . 55 10.5.4.4 bitphase register . . . . . . . . . . . . . . . . . . . . . . 56 10.5.4.5 rxthreshold register . . . . . . . . . . . . . . . . . . . 56 10.5.4.6 preset1d register . . . . . . . . . . . . . . . . . . . . . 56 10.5.4.7 rxcontrol2 register. . . . . . . . . . . . . . . . . . . . . 57 10.5.4.8 clockqcontrol register . . . . . . . . . . . . . . . . . . 57 10.5.5 page 4: rf timing and channel redundancy . 58 10.5.5.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.5.5.2 rxwait register . . . . . . . . . . . . . . . . . . . . . . . . 58 10.5.5.3 channelredundancy register . . . . . . . . . . . . . 58 10.5.5.4 crcpresetlsb register . . . . . . . . . . . . . . . . . 59 10.5.5.5 crcpresetmsb register. . . . . . . . . . . . . . . . . 59 10.5.5.6 preset25 register . . . . . . . . . . . . . . . . . . . . . . 59 10.5.5.7 mfoutselect register . . . . . . . . . . . . . . . . . . 60 10.5.5.8 preset27 register . . . . . . . . . . . . . . . . . . . . . . 60 10.5.6 page 5: fifo, timer and irq pin configuration 61 10.5.6.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.5.6.2 fifolevel register . . . . . . . . . . . . . . . . . . . . . 61 10.5.6.3 timerclock register . . . . . . . . . . . . . . . . . . . . 61 10.5.6.4 timercontrol register . . . . . . . . . . . . . . . . . . . 62 10.5.6.5 timerreload register . . . . . . . . . . . . . . . . . . . 62 10.5.6.6 irqpinconfig register . . . . . . . . . . . . . . . . . . 63 10.5.6.7 preset2e register. . . . . . . . . . . . . . . . . . . . . . 63 10.5.6.8 preset2f register. . . . . . . . . . . . . . . . . . . . . . 63 10.5.7 page 6: reserved . . . . . . . . . . . . . . . . . . . . . . 63 10.5.7.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.5.7.2 reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.5.8 page 7: test control . . . . . . . . . . . . . . . . . . . . 64 10.5.8.1 page register . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.5.8.2 reserved register 39h . . . . . . . . . . . . . . . . . . 64 10.5.8.3 testanaselect register . . . . . . . . . . . . . . . . . . 64 10.5.8.4 reserved register 3bh . . . . . . . . . . . . . . . . . . 65 10.5.8.5 reserved register 3ch . . . . . . . . . . . . . . . . . . 65 10.5.8.6 testdigiselect register . . . . . . . . . . . . . . . . . . 65 10.5.8.7 reserved registers 3eh, 3fh . . . . . . . . . . . . . 66 11 mfrc500 command set . . . . . . . . . . . . . . . . . 66 11.1 mfrc500 command overview. . . . . . . . . . . . 66 11.1.1 basic states . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.1.2 startup command 3fh . . . . . . . . . . . . . . . . . . 68 11.1.3 idle command 00h . . . . . . . . . . . . . . . . . . . . . 68 11.2 commands for card communication . . . . . . . 69 11.2.1 transmit command 1ah . . . . . . . . . . . . . . . . . 69 11.2.1.1 using the transmit command . . . . . . . . . . . . 69 11.2.1.2 rf channel redundancy and framing. . . . . . . 70 11.2.1.3 transmission of bit oriented frames . . . . . . . . 70 11.2.1.4 transmission of frames with more than 64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.2.2 receive command 16h . . . . . . . . . . . . . . . . . 72 11.2.2.1 using the receive command . . . . . . . . . . . . . 72 11.2.2.2 rf channel redundancy and framing. . . . . . . 73 11.2.2.3 collision detection . . . . . . . . . . . . . . . . . . . . . 73 11.2.2.4 receiving bit oriented frames . . . . . . . . . . . . 74 11.2.2.5 communication errors . . . . . . . . . . . . . . . . . . 74 11.2.3 transceive command 1eh . . . . . . . . . . . . . . . 75 11.2.4 card communication states . . . . . . . . . . . . . . 75 11.2.5 card communication state diagram . . . . . . . . 76 11.3 eeprom commands. . . . . . . . . . . . . . . . . . . 77 11.3.1 writee2 command 01h . . . . . . . . . . . . . . . . . 77 11.3.1.1 programming process . . . . . . . . . . . . . . . . . . 77 11.3.1.2 timing diagram . . . . . . . . . . . . . . . . . . . . . . . 78 11.3.1.3 writee2 command error flags . . . . . . . . . . . . 78 11.3.2 reade2 command 03h . . . . . . . . . . . . . . . . . 79 11.3.2.1 reade2 command error flags . . . . . . . . . . . . 79 11.4 diverse commands . . . . . . . . . . . . . . . . . . . . 79 11.4.1 loadconfig command 07h. . . . . . . . . . . . . . . 79
nxp semiconductors mfrc500 the "original" mifare reader solution ? nxp b.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 11 february 2014 048034 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 11.4.1.1 register assignment . . . . . . . . . . . . . . . . . . . . 79 11.4.1.2 relevant loadconfig command error flags . . 80 11.4.2 calccrc command 12h . . . . . . . . . . . . . . . . . 80 11.4.2.1 crc coprocessor settings . . . . . . . . . . . . . . . 80 11.4.2.2 crc coprocessor status flags . . . . . . . . . . . . 80 11.5 error handling during command execution . . . 81 11.6 mifare security commands . . . . . . . . . . . . . 81 11.6.1 loadkeye2 command 0bh . . . . . . . . . . . . . . . 81 11.6.1.1 relevant loadkeye2 command error flags . . 81 11.6.2 loadkey command 19h . . . . . . . . . . . . . . . . . 81 11.6.2.1 relevant loadkey command error flags . . . . 82 11.6.3 authent1 command 0ch . . . . . . . . . . . . . . . . . 82 11.6.4 authent2 command 14h . . . . . . . . . . . . . . . . . 82 11.6.4.1 authent2 command effects . . . . . . . . . . . . . . . 83 12 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 83 13 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.1 operating condition range . . . . . . . . . . . . . . . 83 13.2 current consumption . . . . . . . . . . . . . . . . . . . 84 13.3 pin characteristics . . . . . . . . . . . . . . . . . . . . . 84 13.3.1 input pin characteristics . . . . . . . . . . . . . . . . . 84 13.3.2 digital output pin characteristics . . . . . . . . . . . 85 13.3.3 antenna driver output pin characteristics . . . . 86 13.4 ac electrical characteristi cs . . . . . . . . . . . . . . 86 13.4.1 separate read/write strobe bus timing . . . . . . 86 13.4.2 common read/write strobe bus timing . . . . . . 87 13.4.3 epp bus timing . . . . . . . . . . . . . . . . . . . . . . . . 88 13.4.4 clock frequency . . . . . . . . . . . . . . . . . . . . . . . 90 14 eeprom characteristics . . . . . . . . . . . . . . . . . 90 15 application information. . . . . . . . . . . . . . . . . . 91 15.1 typical application . . . . . . . . . . . . . . . . . . . . . 91 15.1.1 circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . 91 15.1.2 circuit description . . . . . . . . . . . . . . . . . . . . . . 91 15.1.2.1 emc low-pass filter. . . . . . . . . . . . . . . . . . . . . 91 15.1.2.2 antenna matching. . . . . . . . . . . . . . . . . . . . . . 92 15.1.2.3 receiver circuit . . . . . . . . . . . . . . . . . . . . . . . . 92 15.1.2.4 antenna coil . . . . . . . . . . . . . . . . . . . . . . . . . . 93 15.2 test signals. . . . . . . . . . . . . . . . . . . . . . . . . . . 93 15.2.1 measurements using the serial signal switch . 94 15.2.1.1 tx control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 15.2.1.2 rx control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 15.2.2 analog test signals . . . . . . . . . . . . . . . . . . . . . 96 15.2.3 digital test signals. . . . . . . . . . . . . . . . . . . . . . 97 15.2.4 analog and digital test signal examples . . . . . 97 16 package outline . . . . . . . . . . . . . . . . . . . . . . . . 99 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 100 18 references . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 101 20 legal information. . . . . . . . . . . . . . . . . . . . . . 102 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 102 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 102 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 102 20.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 103 21 contact information . . . . . . . . . . . . . . . . . . . 103 22 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 23 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 24 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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